Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6635896 [patent_doc_number] => 20030006500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Circuit board, method for manufacturing same, and high-output module' [patent_app_type] => new [patent_app_number] => 10/186727 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2982 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006500.pdf [firstpage_image] =>[orig_patent_app_number] => 10186727 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186727
Circuit board, method for manufacturing same, and high-output module Jul 1, 2002 Abandoned
Array ( [id] => 6713842 [patent_doc_number] => 20030025190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Tape ball grid array semiconductor chip package having ball land pad isolated from adhesive, a method of manufacturing the same and a multi-chip package' [patent_app_type] => new [patent_app_number] => 10/186617 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3744 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20030025190.pdf [firstpage_image] =>[orig_patent_app_number] => 10186617 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186617
Tape ball grid array semiconductor chip package having ball land pad isolated from adhesive, a method of manufacturing the same and a multi-chip package Jul 1, 2002 Abandoned
Array ( [id] => 6635834 [patent_doc_number] => 20030006494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Thin profile stackable semiconductor package and method for manufacturing' [patent_app_type] => new [patent_app_number] => 10/186407 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 8734 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006494.pdf [firstpage_image] =>[orig_patent_app_number] => 10186407 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186407
Thin profile stackable semiconductor package and method for manufacturing Jun 27, 2002 Abandoned
Array ( [id] => 1037832 [patent_doc_number] => 06872984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-29 [patent_title] => 'Method of sealing a hermetic lid to a semiconductor die at an angle' [patent_app_type] => utility [patent_app_number] => 10/179664 [patent_app_country] => US [patent_app_date] => 2002-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 5900 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872984.pdf [firstpage_image] =>[orig_patent_app_number] => 10179664 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/179664
Method of sealing a hermetic lid to a semiconductor die at an angle Jun 23, 2002 Issued
Array ( [id] => 6494558 [patent_doc_number] => 20020190359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Active device assembly' [patent_app_type] => new [patent_app_number] => 10/169007 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5355 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190359.pdf [firstpage_image] =>[orig_patent_app_number] => 10169007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/169007
Active device assembly Jun 20, 2002 Abandoned
Array ( [id] => 6647138 [patent_doc_number] => 20030075788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Stacked semiconductor package and fabricating method thereof' [patent_app_type] => new [patent_app_number] => 10/175827 [patent_app_country] => US [patent_app_date] => 2002-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2440 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20030075788.pdf [firstpage_image] =>[orig_patent_app_number] => 10175827 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/175827
Stacked semiconductor package and fabricating method thereof Jun 20, 2002 Abandoned
Array ( [id] => 5787472 [patent_doc_number] => 20020160602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Method for forming metal wiring layer' [patent_app_type] => new [patent_app_number] => 10/174378 [patent_app_country] => US [patent_app_date] => 2002-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4188 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160602.pdf [firstpage_image] =>[orig_patent_app_number] => 10174378 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/174378
Method for forming metal wiring layer Jun 17, 2002 Abandoned
Array ( [id] => 6772455 [patent_doc_number] => 20030015793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Microstructure control of copper interconnects' [patent_app_type] => new [patent_app_number] => 10/152879 [patent_app_country] => US [patent_app_date] => 2002-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1361 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015793.pdf [firstpage_image] =>[orig_patent_app_number] => 10152879 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/152879
Microstructure control of copper interconnects May 20, 2002 Abandoned
Array ( [id] => 6755832 [patent_doc_number] => 20030003609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Ultra-fast nucleic acid sequencing device and a method for making and using the same' [patent_app_type] => new [patent_app_number] => 10/143568 [patent_app_country] => US [patent_app_date] => 2002-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6834 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003609.pdf [firstpage_image] =>[orig_patent_app_number] => 10143568 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/143568
Ultra-fast nucleic acid sequencing device and a method for making and using the same May 12, 2002 Abandoned
Array ( [id] => 1271015 [patent_doc_number] => 06648928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-18 [patent_title] => 'Method of making an implantable medical device having a flat electrolytic capacitor with miniaturized epoxy connector droplet' [patent_app_type] => B2 [patent_app_number] => 10/136799 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 39 [patent_no_of_words] => 19891 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/648/06648928.pdf [firstpage_image] =>[orig_patent_app_number] => 10136799 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/136799
Method of making an implantable medical device having a flat electrolytic capacitor with miniaturized epoxy connector droplet Apr 29, 2002 Issued
Array ( [id] => 5782868 [patent_doc_number] => 20020158310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Insulating film of semiconductor device and coating solution for forming insulating film and method of manufacturing insulating film' [patent_app_type] => new [patent_app_number] => 10/133321 [patent_app_country] => US [patent_app_date] => 2002-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6413 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158310.pdf [firstpage_image] =>[orig_patent_app_number] => 10133321 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/133321
Method of forming an insulating film having SI-C, SI-O and SI-H bonds to cover wiringlines of a semiconductor device Apr 28, 2002 Issued
Array ( [id] => 1133805 [patent_doc_number] => 06783994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Method of fabricating a self-aligned magnetic tunneling junction and via contact' [patent_app_type] => B2 [patent_app_number] => 10/133136 [patent_app_country] => US [patent_app_date] => 2002-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 2882 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/783/06783994.pdf [firstpage_image] =>[orig_patent_app_number] => 10133136 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/133136
Method of fabricating a self-aligned magnetic tunneling junction and via contact Apr 25, 2002 Issued
Array ( [id] => 5782846 [patent_doc_number] => 20020158301 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Semiconductor substrate with smooth trench' [patent_app_type] => new [patent_app_number] => 10/132298 [patent_app_country] => US [patent_app_date] => 2002-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11659 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20020158301.pdf [firstpage_image] =>[orig_patent_app_number] => 10132298 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/132298
Semiconductor substrate formed by epitaxially filling a trench in a semiconductor substrate with a semiconductor material after smoothing the surface and rounding the corners Apr 25, 2002 Issued
Array ( [id] => 6636511 [patent_doc_number] => 20030211729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Method of fabricating a sub-lithographic sized via' [patent_app_type] => new [patent_app_number] => 10/133605 [patent_app_country] => US [patent_app_date] => 2002-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3669 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20030211729.pdf [firstpage_image] =>[orig_patent_app_number] => 10133605 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/133605
Method of fabricating a sub-lithographic sized via Apr 24, 2002 Issued
Array ( [id] => 1281101 [patent_doc_number] => 06642131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-04 [patent_title] => 'METHOD OF FORMING A SILICON-CONTAINING METAL-OXIDE GATE DIELECTRIC BY DEPOSITING A HIGH DIELECTRIC CONSTANT FILM ON A SILICON SUBSTRATE AND DIFFUSING SILICON FROM THE SUBSTRATE INTO THE HIGH DIELECTRIC CONSTANT FILM' [patent_app_type] => B2 [patent_app_number] => 10/122366 [patent_app_country] => US [patent_app_date] => 2002-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 13738 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/642/06642131.pdf [firstpage_image] =>[orig_patent_app_number] => 10122366 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/122366
METHOD OF FORMING A SILICON-CONTAINING METAL-OXIDE GATE DIELECTRIC BY DEPOSITING A HIGH DIELECTRIC CONSTANT FILM ON A SILICON SUBSTRATE AND DIFFUSING SILICON FROM THE SUBSTRATE INTO THE HIGH DIELECTRIC CONSTANT FILM Apr 15, 2002 Issued
Array ( [id] => 1277880 [patent_doc_number] => 06645838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Selective absorption process for forming an activated doped region in a semiconductor' [patent_app_type] => B1 [patent_app_number] => 10/122955 [patent_app_country] => US [patent_app_date] => 2002-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6770 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/645/06645838.pdf [firstpage_image] =>[orig_patent_app_number] => 10122955 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/122955
Selective absorption process for forming an activated doped region in a semiconductor Apr 10, 2002 Issued
Array ( [id] => 1205765 [patent_doc_number] => 06716771 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface' [patent_app_type] => B2 [patent_app_number] => 10/119805 [patent_app_country] => US [patent_app_date] => 2002-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2648 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716771.pdf [firstpage_image] =>[orig_patent_app_number] => 10119805 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/119805
Method for post-CMP conversion of a hydrophobic surface of a low-k dielectric layer to a hydrophilic surface Apr 8, 2002 Issued
Array ( [id] => 1235780 [patent_doc_number] => 06689691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-10 [patent_title] => 'Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a polishing installation' [patent_app_type] => B2 [patent_app_number] => 10/117826 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 15 [patent_no_of_words] => 3770 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/689/06689691.pdf [firstpage_image] =>[orig_patent_app_number] => 10117826 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/117826
Method of simultaneously polishing a plurality of objects of a similar type, in particular silicon wafers, on a polishing installation Apr 7, 2002 Issued
Array ( [id] => 5986170 [patent_doc_number] => 20020098599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Method of manufacturing ferroelectric memory device' [patent_app_type] => new [patent_app_number] => 10/108381 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4828 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098599.pdf [firstpage_image] =>[orig_patent_app_number] => 10108381 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/108381
Method of manufacturing ferroelectric memory device Mar 28, 2002 Abandoned
Array ( [id] => 6829931 [patent_doc_number] => 20030180989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Method for making nanoscale wires and gaps for switches and transistors' [patent_app_type] => new [patent_app_number] => 10/104348 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2069 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20030180989.pdf [firstpage_image] =>[orig_patent_app_number] => 10104348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/104348
Method for making nanoscale wires and gaps for switches and transistors Mar 21, 2002 Issued
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