Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1507561 [patent_doc_number] => 06440876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Low-K dielectric constant CVD precursors formed of cyclic siloxanes having in-ring SIOC, and uses thereof' [patent_app_type] => B1 [patent_app_number] => 09/971837 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3678 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440876.pdf [firstpage_image] =>[orig_patent_app_number] => 09971837 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/971837
Low-K dielectric constant CVD precursors formed of cyclic siloxanes having in-ring SIOC, and uses thereof Oct 4, 2001 Issued
Array ( [id] => 1327914 [patent_doc_number] => 06603150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Organic light-emitting diode having an interface layer between the hole-transporting layer and the light-emitting layer' [patent_app_type] => B2 [patent_app_number] => 09/966618 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 4682 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603150.pdf [firstpage_image] =>[orig_patent_app_number] => 09966618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966618
Organic light-emitting diode having an interface layer between the hole-transporting layer and the light-emitting layer Sep 27, 2001 Issued
Array ( [id] => 6673932 [patent_doc_number] => 20030059535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Cycling deposition of low temperature films in a cold wall single wafer process chamber' [patent_app_type] => new [patent_app_number] => 09/964075 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7353 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20030059535.pdf [firstpage_image] =>[orig_patent_app_number] => 09964075 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964075
Cycling deposition of low temperature films in a cold wall single wafer process chamber Sep 24, 2001 Abandoned
Array ( [id] => 6635670 [patent_doc_number] => 20030006477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Porous materials' [patent_app_type] => new [patent_app_number] => 09/961808 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 12089 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006477.pdf [firstpage_image] =>[orig_patent_app_number] => 09961808 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961808
Porous materials Sep 23, 2001 Abandoned
Array ( [id] => 5888708 [patent_doc_number] => 20020013037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Two-dimensionally arrayed quantum device' [patent_app_type] => new [patent_app_number] => 09/956823 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6121 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013037.pdf [firstpage_image] =>[orig_patent_app_number] => 09956823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956823
Method of forming a two-dimensionally arrayed quantum device using a metalloprotein complex as a quantum-dot mask array Sep 20, 2001 Issued
Array ( [id] => 6720939 [patent_doc_number] => 20030054628 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Method of forming a low resistance multi-layered TiN film with superior barrier property using poison mode cycling' [patent_app_type] => new [patent_app_number] => 09/953545 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2434 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054628.pdf [firstpage_image] =>[orig_patent_app_number] => 09953545 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953545
Method of forming a low resistance multi-layered TiN film with superior barrier property using poison mode cycling Sep 16, 2001 Abandoned
Array ( [id] => 6033064 [patent_doc_number] => 20020019142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-14 [patent_title] => 'Methods of forming transistors associated with semiconductor substrates' [patent_app_type] => new [patent_app_number] => 09/951152 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3215 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20020019142.pdf [firstpage_image] =>[orig_patent_app_number] => 09951152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951152
Methods of forming transistors associated with semiconductor substrates Sep 11, 2001 Issued
Array ( [id] => 6284825 [patent_doc_number] => 20020053653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Low dielectric constant film having thermal resistance, process for forming the same, insulation film between semiconductor layer using the same, and semiconductor device' [patent_app_type] => new [patent_app_number] => 09/941766 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2726 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20020053653.pdf [firstpage_image] =>[orig_patent_app_number] => 09941766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/941766
LOW DIELECTRIC CONSTANT FILM COMPOSED OF BORON, NITROGEN, AND HYDROGEN HAVING THERMAL RESISTANCE, PROCESS FOR FORMING THE FILM, USE OF THE FILM BETWEEN SEMICONDUCTOR DEVICE LAYERS, AND THE DEVICE FORMED FROM THE FILM Aug 29, 2001 Issued
Array ( [id] => 1413097 [patent_doc_number] => 06524976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method of heat-treating nitride compound semiconductor layer and method of producing semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/924615 [patent_app_country] => US [patent_app_date] => 2001-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6018 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/524/06524976.pdf [firstpage_image] =>[orig_patent_app_number] => 09924615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924615
Method of heat-treating nitride compound semiconductor layer and method of producing semiconductor device Aug 8, 2001 Issued
Array ( [id] => 1288857 [patent_doc_number] => 06632736 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer' [patent_app_type] => B2 [patent_app_number] => 09/921615 [patent_app_country] => US [patent_app_date] => 2001-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3847 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632736.pdf [firstpage_image] =>[orig_patent_app_number] => 09921615 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921615
Method of forming low-resistance contact to silicon having a titanium silicide interface and an amorphous titanium carbonitride barrier layer Aug 2, 2001 Issued
Array ( [id] => 1602641 [patent_doc_number] => 06432820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of selectively depositing a metal layer in an opening in a dielectric layer by forming a metal-deposition-prevention layer around the opening of the dielectric layer' [patent_app_type] => B1 [patent_app_number] => 09/921165 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4142 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432820.pdf [firstpage_image] =>[orig_patent_app_number] => 09921165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/921165
Method of selectively depositing a metal layer in an opening in a dielectric layer by forming a metal-deposition-prevention layer around the opening of the dielectric layer Aug 1, 2001 Issued
Array ( [id] => 6742980 [patent_doc_number] => 20030020163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Bonding pad structure for copper/low-k dielectric material BEOL process' [patent_app_type] => new [patent_app_number] => 09/912838 [patent_app_country] => US [patent_app_date] => 2001-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3258 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20030020163.pdf [firstpage_image] =>[orig_patent_app_number] => 09912838 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/912838
Bonding pad structure for copper/low-k dielectric material BEOL process Jul 24, 2001 Abandoned
Array ( [id] => 6092053 [patent_doc_number] => 20020050626 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-02 [patent_title] => 'Semiconductor device and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 09/907026 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3541 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20020050626.pdf [firstpage_image] =>[orig_patent_app_number] => 09907026 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907026
Semiconductor device and manufacturing method therefor Jul 16, 2001 Abandoned
Array ( [id] => 1440130 [patent_doc_number] => 06495460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface' [patent_app_type] => B1 [patent_app_number] => 09/901705 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4622 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495460.pdf [firstpage_image] =>[orig_patent_app_number] => 09901705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901705
Dual layer silicide formation using a titanium barrier to reduce surface roughness at silicide/junction interface Jul 10, 2001 Issued
Array ( [id] => 6474586 [patent_doc_number] => 20020022366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow Junctions' [patent_app_type] => new [patent_app_number] => 09/902483 [patent_app_country] => US [patent_app_date] => 2001-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7025 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20020022366.pdf [firstpage_image] =>[orig_patent_app_number] => 09902483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902483
Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctions Jul 10, 2001 Issued
Array ( [id] => 1110400 [patent_doc_number] => 06809788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-26 [patent_title] => 'Liquid crystal display element with different ratios of polydomain and monodomain states' [patent_app_type] => B2 [patent_app_number] => 09/896873 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 73 [patent_no_of_words] => 45538 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/809/06809788.pdf [firstpage_image] =>[orig_patent_app_number] => 09896873 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896873
Liquid crystal display element with different ratios of polydomain and monodomain states Jun 28, 2001 Issued
Array ( [id] => 6139234 [patent_doc_number] => 20020001054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Color type liquid crystal display having a high aperture ratio' [patent_app_type] => new [patent_app_number] => 09/894231 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1004 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001054.pdf [firstpage_image] =>[orig_patent_app_number] => 09894231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894231
Color type liquid crystal display having a high aperture ratio Jun 27, 2001 Abandoned
Array ( [id] => 1247412 [patent_doc_number] => 06678027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Fringe field switching mode LCD' [patent_app_type] => B2 [patent_app_number] => 09/894937 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2228 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678027.pdf [firstpage_image] =>[orig_patent_app_number] => 09894937 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894937
Fringe field switching mode LCD Jun 27, 2001 Issued
Array ( [id] => 6141844 [patent_doc_number] => 20020001946 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Method and fabricating metal interconnection with reliability using ionized physical vapor deposition' [patent_app_type] => new [patent_app_number] => 09/892536 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2136 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001946.pdf [firstpage_image] =>[orig_patent_app_number] => 09892536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/892536
Method and fabricating metal interconnection with reliability using ionized physical vapor deposition Jun 27, 2001 Abandoned
Array ( [id] => 6755969 [patent_doc_number] => 20030003746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Process of providing a semiconductor device with electrical interconnection capability' [patent_app_type] => new [patent_app_number] => 09/893266 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1992 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003746.pdf [firstpage_image] =>[orig_patent_app_number] => 09893266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893266
Process of providing a semiconductor device with electrical interconnection capability Jun 26, 2001 Issued
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