Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1096009 [patent_doc_number] => 06821862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES THAT INCLUDE A METAL OXIDE LAYER DISPOSED ON ANOTHER LAYER TO PROTECT THE OTHER LAYER FROM DIFFUSION OF IMPURITIES AND INTEGRATED CIRCUIT DEVICES MANUFACTURED USING SAME' [patent_app_type] => B2 [patent_app_number] => 09/893035 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4829 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/821/06821862.pdf [firstpage_image] =>[orig_patent_app_number] => 09893035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893035
METHODS OF MANUFACTURING INTEGRATED CIRCUIT DEVICES THAT INCLUDE A METAL OXIDE LAYER DISPOSED ON ANOTHER LAYER TO PROTECT THE OTHER LAYER FROM DIFFUSION OF IMPURITIES AND INTEGRATED CIRCUIT DEVICES MANUFACTURED USING SAME Jun 26, 2001 Issued
Array ( [id] => 954103 [patent_doc_number] => 06958518 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor' [patent_app_type] => utility [patent_app_number] => 09/882624 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3818 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958518.pdf [firstpage_image] =>[orig_patent_app_number] => 09882624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/882624
Semiconductor device having at least one source/drain region formed on an isolation region and a method of manufacture therefor Jun 14, 2001 Issued
Array ( [id] => 6063654 [patent_doc_number] => 20020031911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Method of manufacturing a copper metal wiring in a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/880815 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2017 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0031/20020031911.pdf [firstpage_image] =>[orig_patent_app_number] => 09880815 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/880815
Method of manufacturing a copper metal wiring in a semiconductor device Jun 14, 2001 Issued
Array ( [id] => 5856278 [patent_doc_number] => 20020121638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-05 [patent_title] => 'Electroluminescent iridium compounds with fluorinated phenylpyridines, phenylpyrimidines, and phenylquinolines and devices made with such compounds' [patent_app_type] => new [patent_app_number] => 09/879014 [patent_app_country] => US [patent_app_date] => 2001-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 9944 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20020121638.pdf [firstpage_image] =>[orig_patent_app_number] => 09879014 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/879014
Electroluminescent iridium compounds with fluorinated phenylpyridines, phenylpyrimidines, and phenylquinolines and devices made with such compounds Jun 11, 2001 Abandoned
Array ( [id] => 7000654 [patent_doc_number] => 20010053603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Method of manufacturing a copper metal wiring in a semiconductor device' [patent_app_type] => new [patent_app_number] => 09/875625 [patent_app_country] => US [patent_app_date] => 2001-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1899 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053603.pdf [firstpage_image] =>[orig_patent_app_number] => 09875625 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875625
Method of catalyzing copper deposition in a damascene structure by plasma treating the barrier layer and then applying a catalyst such as iodine or iodine compounds to the barrier layer Jun 5, 2001 Issued
Array ( [id] => 6986919 [patent_doc_number] => 20010036751 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-01 [patent_title] => 'Method for forming a thin oxide layer using wet oxidation' [patent_app_type] => new [patent_app_number] => 09/874267 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4154 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20010036751.pdf [firstpage_image] =>[orig_patent_app_number] => 09874267 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874267
Method for forming a thin oxide layer using wet oxidation Jun 3, 2001 Abandoned
Array ( [id] => 6889430 [patent_doc_number] => 20010024885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Substrate for semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 09/871674 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3796 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024885.pdf [firstpage_image] =>[orig_patent_app_number] => 09871674 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871674
Substrate for semiconductor device and method of manufacturing the same Jun 3, 2001 Abandoned
Array ( [id] => 933819 [patent_doc_number] => 06977014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-20 [patent_title] => 'Architecture for high throughput semiconductor processing applications' [patent_app_type] => utility [patent_app_number] => 09/872796 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7869 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977014.pdf [firstpage_image] =>[orig_patent_app_number] => 09872796 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872796
Architecture for high throughput semiconductor processing applications May 31, 2001 Issued
Array ( [id] => 6882710 [patent_doc_number] => 20010049182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Manufacturing method of semiconductor substrate' [patent_app_type] => new [patent_app_number] => 09/870705 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11724 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049182.pdf [firstpage_image] =>[orig_patent_app_number] => 09870705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870705
Method of improving epitaxially-filled trench by smoothing trench prior to filling May 31, 2001 Issued
Array ( [id] => 6409401 [patent_doc_number] => 20020182860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method of forming self-aligned silicide layers on semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/865516 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1018 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182860.pdf [firstpage_image] =>[orig_patent_app_number] => 09865516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865516
Method of forming self-aligned silicide layers on semiconductor devices May 28, 2001 Abandoned
Array ( [id] => 6447531 [patent_doc_number] => 20020177308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method for surface treatment protecting metallic surface of semiconductor structure' [patent_app_type] => new [patent_app_number] => 09/862496 [patent_app_country] => US [patent_app_date] => 2001-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1456 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177308.pdf [firstpage_image] =>[orig_patent_app_number] => 09862496 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/862496
Method for surface treatment protecting metallic surface of semiconductor structure May 22, 2001 Abandoned
Array ( [id] => 6447699 [patent_doc_number] => 20020177327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method for forming a gate dielectric layer by a single wafer process' [patent_app_type] => new [patent_app_number] => 09/861655 [patent_app_country] => US [patent_app_date] => 2001-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2357 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20020177327.pdf [firstpage_image] =>[orig_patent_app_number] => 09861655 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/861655
Method for forming a gate dielectric layer by a single wafer process May 21, 2001 Abandoned
Array ( [id] => 1027953 [patent_doc_number] => 06881669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Process for making electronic devices having a monolayer diffusion barrier' [patent_app_type] => utility [patent_app_number] => 09/853925 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 10318 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/881/06881669.pdf [firstpage_image] =>[orig_patent_app_number] => 09853925 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853925
Process for making electronic devices having a monolayer diffusion barrier May 8, 2001 Issued
Array ( [id] => 5951421 [patent_doc_number] => 20020006675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-17 [patent_title] => 'Semiconductor manufacturing apparatus and method of manufacturing semiconductor devices' [patent_app_type] => new [patent_app_number] => 09/851158 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6723 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20020006675.pdf [firstpage_image] =>[orig_patent_app_number] => 09851158 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851158
Semiconductor manufacturing apparatus and method of manufacturing semiconductor devices May 8, 2001 Abandoned
Array ( [id] => 6081242 [patent_doc_number] => 20020081846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 09/851095 [patent_app_country] => US [patent_app_date] => 2001-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5368 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20020081846.pdf [firstpage_image] =>[orig_patent_app_number] => 09851095 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851095
Semiconductor device May 8, 2001 Abandoned
Array ( [id] => 6886633 [patent_doc_number] => 20010019902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Wet-oxidation apparatus and wet-oxidation method' [patent_app_type] => new [patent_app_number] => 09/849516 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6622 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019902.pdf [firstpage_image] =>[orig_patent_app_number] => 09849516 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/849516
Wet-oxidation apparatus and wet-oxidation method May 6, 2001 Abandoned
Array ( [id] => 1341762 [patent_doc_number] => 06586348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation anneal but while still amorphous and then thermally annealing to crystallize' [patent_app_type] => B2 [patent_app_number] => 09/850585 [patent_app_country] => US [patent_app_date] => 2001-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3325 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586348.pdf [firstpage_image] =>[orig_patent_app_number] => 09850585 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850585
Method for preventing etching-induced damage to a metal oxide film by patterning the film after a nucleation anneal but while still amorphous and then thermally annealing to crystallize May 6, 2001 Issued
Array ( [id] => 1285283 [patent_doc_number] => 06638851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-28 [patent_title] => 'Dual hardmask single damascene integration scheme in an organic low k ILD' [patent_app_type] => B2 [patent_app_number] => 09/845305 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 2167 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638851.pdf [firstpage_image] =>[orig_patent_app_number] => 09845305 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845305
Dual hardmask single damascene integration scheme in an organic low k ILD Apr 30, 2001 Issued
Array ( [id] => 6111522 [patent_doc_number] => 20020173169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Two-step flourinated-borophosophosilicate glass deposition process' [patent_app_type] => new [patent_app_number] => 09/832756 [patent_app_country] => US [patent_app_date] => 2001-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5005 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20020173169.pdf [firstpage_image] =>[orig_patent_app_number] => 09832756 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/832756
Two-step flourinated-borophosophosilicate glass deposition process Apr 9, 2001 Abandoned
Array ( [id] => 1565514 [patent_doc_number] => 06376260 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Magnetic element with improved field response and fabricating method thereof' [patent_app_type] => B1 [patent_app_number] => 09/825705 [patent_app_country] => US [patent_app_date] => 2001-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3033 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376260.pdf [firstpage_image] =>[orig_patent_app_number] => 09825705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/825705
Magnetic element with improved field response and fabricating method thereof Apr 4, 2001 Issued
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