
Charles E. Cooley
Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )
| Most Active Art Unit | 1774 |
| Art Unit(s) | 1797, 1754, 3405, 2402, 1774, 1723 |
| Total Applications | 4068 |
| Issued Applications | 3145 |
| Pending Applications | 298 |
| Abandoned Applications | 660 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6986889
[patent_doc_number] => 20010036721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-01
[patent_title] => 'Process for metallizing at least one insulating layer of a component'
[patent_app_type] => new
[patent_app_number] => 09/817966
[patent_app_country] => US
[patent_app_date] => 2001-03-27
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4489
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0036/20010036721.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/817966 | Process for metallizing at least one insulating layer of a component | Mar 26, 2001 | Abandoned |
Array
(
[id] => 7645670
[patent_doc_number] => 06472299
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-10-29
[patent_title] => 'Method and apparatus for treating a substrate with hydrogen radicals at a temperature of less than 40 K'
[patent_app_type] => B2
[patent_app_number] => 09/811785
[patent_app_country] => US
[patent_app_date] => 2001-03-20
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Array
(
[id] => 5844620
[patent_doc_number] => 20020132473
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[patent_kind] => A1
[patent_issue_date] => 2002-09-19
[patent_title] => 'Integrated barrier layer structure for copper contact level metallization'
[patent_app_type] => new
[patent_app_number] => 09/805865
[patent_app_country] => US
[patent_app_date] => 2001-03-13
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/805865 | Integrated barrier layer structure for copper contact level metallization | Mar 12, 2001 | Abandoned |
Array
(
[id] => 6921623
[patent_doc_number] => 20010029108
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-11
[patent_title] => 'Substrate processeing apparatus, substrate processing method and electronic device manufacturing method'
[patent_app_type] => new
[patent_app_number] => 09/799816
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[patent_app_date] => 2001-03-05
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Array
(
[id] => 6379041
[patent_doc_number] => 20020119644
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[patent_kind] => A1
[patent_issue_date] => 2002-08-29
[patent_title] => 'Method of controlling crystallographic orientation in laser-annealed polycrystalline silicon films'
[patent_app_type] => new
[patent_app_number] => 09/796345
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[patent_app_date] => 2001-02-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/796345 | Method of controlling crystallographic orientation in laser-annealed polycrystalline silicon films | Feb 27, 2001 | Issued |
Array
(
[id] => 1474525
[patent_doc_number] => 06387762
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[patent_issue_date] => 2002-05-14
[patent_title] => 'Method of manufacturing ferroelectric memory device'
[patent_app_type] => B2
[patent_app_number] => 09/791616
[patent_app_country] => US
[patent_app_date] => 2001-02-26
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[firstpage_image] =>[orig_patent_app_number] => 09791616
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/791616 | Method of manufacturing ferroelectric memory device | Feb 25, 2001 | Issued |
Array
(
[id] => 5922065
[patent_doc_number] => 20020115283
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[patent_kind] => A1
[patent_issue_date] => 2002-08-22
[patent_title] => 'Planarization by selective electro-dissolution'
[patent_app_type] => new
[patent_app_number] => 09/785115
[patent_app_country] => US
[patent_app_date] => 2001-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3723
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[pdf_file] => publications/A1/0115/20020115283.pdf
[firstpage_image] =>[orig_patent_app_number] => 09785115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/785115 | Planarization by selective electro-dissolution | Feb 19, 2001 | Abandoned |
Array
(
[id] => 6908187
[patent_doc_number] => 20010010954
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-02
[patent_title] => 'Method of forming an ESD protection device'
[patent_app_type] => new
[patent_app_number] => 09/782024
[patent_app_country] => US
[patent_app_date] => 2001-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => publications/A1/0010/20010010954.pdf
[firstpage_image] =>[orig_patent_app_number] => 09782024
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/782024 | Method of forming an ESD protection device | Feb 13, 2001 | Abandoned |
Array
(
[id] => 5906929
[patent_doc_number] => 20020142589
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-03
[patent_title] => 'Method of obtaining low temperature alpha-ta thin films using wafer bias'
[patent_app_type] => new
[patent_app_number] => 09/775356
[patent_app_country] => US
[patent_app_date] => 2001-01-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/775356 | Method of obtaining low temperature alpha-ta thin films using wafer bias | Jan 30, 2001 | Abandoned |
Array
(
[id] => 1547591
[patent_doc_number] => 06445070
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[patent_kind] => B1
[patent_issue_date] => 2002-09-03
[patent_title] => 'Coherent carbide diffusion barrier for integrated circuit interconnects'
[patent_app_type] => B1
[patent_app_number] => 09/772715
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[patent_app_date] => 2001-01-29
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Array
(
[id] => 1455556
[patent_doc_number] => 06462417
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[patent_title] => 'Coherent alloy diffusion barrier for integrated circuit interconnects'
[patent_app_type] => B1
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Array
(
[id] => 6884724
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[patent_title] => 'Method for forming coating film on a plate-like workpiece'
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Array
(
[id] => 1594630
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[patent_title] => 'Copper vias in low-k technology'
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Array
(
[id] => 6081240
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/740945 | Method for manufacturing a copper interconnection with an aluminum oxide-conductive layer stack barrier layer in semiconductor memory device | Dec 20, 2000 | Issued |
Array
(
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[patent_title] => 'NH3/N2-plasma treatment to prevent organic ILD degradation'
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Array
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Array
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Array
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Array
(
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