Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1415250 [patent_doc_number] => 06518087 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Method for manufacturing solar battery' [patent_app_type] => B1 [patent_app_number] => 09/701646 [patent_app_country] => US [patent_app_date] => 2000-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8120 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518087.pdf [firstpage_image] =>[orig_patent_app_number] => 09701646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/701646
Method for manufacturing solar battery Nov 29, 2000 Issued
Array ( [id] => 1418745 [patent_doc_number] => 06506620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Process for manufacturing micromechanical and microoptomechanical structures with backside metalization' [patent_app_type] => B1 [patent_app_number] => 09/724515 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 6450 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506620.pdf [firstpage_image] =>[orig_patent_app_number] => 09724515 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724515
Process for manufacturing micromechanical and microoptomechanical structures with backside metalization Nov 26, 2000 Issued
09/713026 METHOD OF REDUCING CONTACT RESISTANCE IN A TUNGSTEN INTERCONNECTION BY HYDROGEN-INITROGEN PLASMA TREATMENT OF A PECVD TITANIUM LAYER FOLLOWING BY CVD OF A TITANIUM NITRIDE LAYER Nov 15, 2000 Abandoned
Array ( [id] => 1163443 [patent_doc_number] => 06759324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Method of forming a low resistance contact to underlying aluminum interconnect by depositing titanium in a via opening and reacting the titanium with the aluminum' [patent_app_type] => B1 [patent_app_number] => 09/711270 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4457 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/759/06759324.pdf [firstpage_image] =>[orig_patent_app_number] => 09711270 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/711270
Method of forming a low resistance contact to underlying aluminum interconnect by depositing titanium in a via opening and reacting the titanium with the aluminum Nov 12, 2000 Issued
Array ( [id] => 1553603 [patent_doc_number] => 06348410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Low temperature hillock suppression method in integrated circuit interconnects' [patent_app_type] => B1 [patent_app_number] => 09/705396 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2947 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348410.pdf [firstpage_image] =>[orig_patent_app_number] => 09705396 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705396
Low temperature hillock suppression method in integrated circuit interconnects Nov 1, 2000 Issued
Array ( [id] => 1017941 [patent_doc_number] => 06890835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Layer transfer of low defect SiGe using an etch-back process' [patent_app_type] => utility [patent_app_number] => 09/692606 [patent_app_country] => US [patent_app_date] => 2000-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3054 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890835.pdf [firstpage_image] =>[orig_patent_app_number] => 09692606 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/692606
Layer transfer of low defect SiGe using an etch-back process Oct 18, 2000 Issued
Array ( [id] => 944123 [patent_doc_number] => 06967177 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-22 [patent_title] => 'Temperature control system' [patent_app_type] => utility [patent_app_number] => 09/670975 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5101 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967177.pdf [firstpage_image] =>[orig_patent_app_number] => 09670975 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670975
Temperature control system Sep 26, 2000 Issued
Array ( [id] => 1574733 [patent_doc_number] => 06468885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Deposition of device quality, low hydrogen content, hydrogenated amorphous silicon at high deposition rates' [patent_app_type] => B1 [patent_app_number] => 09/669248 [patent_app_country] => US [patent_app_date] => 2000-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9659 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468885.pdf [firstpage_image] =>[orig_patent_app_number] => 09669248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/669248
Deposition of device quality, low hydrogen content, hydrogenated amorphous silicon at high deposition rates Sep 24, 2000 Issued
09/665898 Semiconductor product with a silver and gold alloy Sep 19, 2000 Abandoned
Array ( [id] => 1302989 [patent_doc_number] => 06620710 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-16 [patent_title] => 'Forming a single crystal semiconductor film on a non-crystalline surface' [patent_app_type] => B1 [patent_app_number] => 09/664916 [patent_app_country] => US [patent_app_date] => 2000-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2909 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/620/06620710.pdf [firstpage_image] =>[orig_patent_app_number] => 09664916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/664916
Forming a single crystal semiconductor film on a non-crystalline surface Sep 17, 2000 Issued
Array ( [id] => 1391897 [patent_doc_number] => 06533874 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'GaN-based devices using thick (Ga, Al, In)N base layers' [patent_app_type] => B1 [patent_app_number] => 09/656595 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 12695 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/533/06533874.pdf [firstpage_image] =>[orig_patent_app_number] => 09656595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/656595
GaN-based devices using thick (Ga, Al, In)N base layers Sep 6, 2000 Issued
Array ( [id] => 1520610 [patent_doc_number] => 06413792 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Ultra-fast nucleic acid sequencing device and a method for making and using the same' [patent_app_type] => B1 [patent_app_number] => 09/653543 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 6746 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413792.pdf [firstpage_image] =>[orig_patent_app_number] => 09653543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653543
Ultra-fast nucleic acid sequencing device and a method for making and using the same Aug 30, 2000 Issued
Array ( [id] => 1580929 [patent_doc_number] => 06423561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/640280 [patent_app_country] => US [patent_app_date] => 2000-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 87 [patent_no_of_words] => 10065 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/423/06423561.pdf [firstpage_image] =>[orig_patent_app_number] => 09640280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/640280
Method for fabricating semiconductor device Aug 15, 2000 Issued
Array ( [id] => 1441064 [patent_doc_number] => 06335272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Buried butted contact and method for fabricating' [patent_app_type] => B1 [patent_app_number] => 09/637935 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2139 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335272.pdf [firstpage_image] =>[orig_patent_app_number] => 09637935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/637935
Buried butted contact and method for fabricating Aug 13, 2000 Issued
Array ( [id] => 1420810 [patent_doc_number] => 06512296 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Semiconductor structure having heterogenous silicide regions having titanium and molybdenum' [patent_app_type] => B1 [patent_app_number] => 09/636325 [patent_app_country] => US [patent_app_date] => 2000-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4539 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512296.pdf [firstpage_image] =>[orig_patent_app_number] => 09636325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/636325
Semiconductor structure having heterogenous silicide regions having titanium and molybdenum Aug 9, 2000 Issued
Array ( [id] => 1550458 [patent_doc_number] => 06399483 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method for improving faceting effect in dual damascene process' [patent_app_type] => B1 [patent_app_number] => 09/624523 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4793 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/399/06399483.pdf [firstpage_image] =>[orig_patent_app_number] => 09624523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624523
Method for improving faceting effect in dual damascene process Jul 23, 2000 Issued
Array ( [id] => 785204 [patent_doc_number] => 06989300 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-01-24 [patent_title] => 'Method for forming semiconductor films at desired positions on a substrate' [patent_app_type] => utility [patent_app_number] => 09/614286 [patent_app_country] => US [patent_app_date] => 2000-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 50 [patent_no_of_words] => 11440 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/989/06989300.pdf [firstpage_image] =>[orig_patent_app_number] => 09614286 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/614286
Method for forming semiconductor films at desired positions on a substrate Jul 11, 2000 Issued
Array ( [id] => 4277945 [patent_doc_number] => 06323532 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Deep divot mask for enhanced buried-channel PFET performance and reliability' [patent_app_type] => 1 [patent_app_number] => 9/609379 [patent_app_country] => US [patent_app_date] => 2000-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3314 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323532.pdf [firstpage_image] =>[orig_patent_app_number] => 609379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/609379
Deep divot mask for enhanced buried-channel PFET performance and reliability Jul 2, 2000 Issued
Array ( [id] => 1382809 [patent_doc_number] => 06551946 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE' [patent_app_type] => B1 [patent_app_number] => 09/597076 [patent_app_country] => US [patent_app_date] => 2000-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6010 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/551/06551946.pdf [firstpage_image] =>[orig_patent_app_number] => 09597076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/597076
TWO-STEP OXIDATION PROCESS FOR OXIDIZING A SILICON SUBSTRATE WHEREIN THE FIRST STEP IS CARRIED OUT AT A TEMPERATURE BELOW THE VISCOELASTIC TEMPERATURE OF SILICON DIOXIDE AND THE SECOND STEP IS CARRIED OUT AT A TEMPERATURE ABOVE THE VISCOELASTIC TEMPERATURE Jun 19, 2000 Issued
Array ( [id] => 1578266 [patent_doc_number] => 06448173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Aluminum-based metallization exhibiting reduced electromigration and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/589546 [patent_app_country] => US [patent_app_date] => 2000-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7065 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448173.pdf [firstpage_image] =>[orig_patent_app_number] => 09589546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/589546
Aluminum-based metallization exhibiting reduced electromigration and method therefor Jun 6, 2000 Issued
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