Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
09/584617 Semiconductor device and a method of manufacturing the same May 30, 2000 Abandoned
Array ( [id] => 4326201 [patent_doc_number] => 06319745 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Formation of charge-coupled-device with image pick-up array' [patent_app_type] => 1 [patent_app_number] => 9/584315 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4178 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319745.pdf [firstpage_image] =>[orig_patent_app_number] => 584315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584315
Formation of charge-coupled-device with image pick-up array May 30, 2000 Issued
Array ( [id] => 1485368 [patent_doc_number] => 06365509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Semiconductor manufacturing method using a dielectric photomask' [patent_app_type] => B1 [patent_app_number] => 09/586556 [patent_app_country] => US [patent_app_date] => 2000-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5454 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365509.pdf [firstpage_image] =>[orig_patent_app_number] => 09586556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586556
Semiconductor manufacturing method using a dielectric photomask May 30, 2000 Issued
Array ( [id] => 1523715 [patent_doc_number] => 06352909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Process for lift-off of a layer from a substrate' [patent_app_type] => B1 [patent_app_number] => 09/578896 [patent_app_country] => US [patent_app_date] => 2000-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4975 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352909.pdf [firstpage_image] =>[orig_patent_app_number] => 09578896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/578896
Process for lift-off of a layer from a substrate May 25, 2000 Issued
Array ( [id] => 1264668 [patent_doc_number] => 06660663 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Computer readable medium for holding a program for performing plasma-assisted CVD of low dielectric constant films formed from organosilane compounds' [patent_app_type] => B1 [patent_app_number] => 09/579819 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 29 [patent_no_of_words] => 9757 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660663.pdf [firstpage_image] =>[orig_patent_app_number] => 09579819 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/579819
Computer readable medium for holding a program for performing plasma-assisted CVD of low dielectric constant films formed from organosilane compounds May 24, 2000 Issued
09/567276 Amorphous metal oxide gate dielectric structure and method thereof May 8, 2000 Abandoned
09/558056 Gas assisted rapid thermal annealing Apr 25, 2000 Abandoned
Array ( [id] => 4357715 [patent_doc_number] => 06255134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method for making high-frame-rate CCD imaging devices from otherwise ordinary and inexpensive CCD devices' [patent_app_type] => 1 [patent_app_number] => 9/558006 [patent_app_country] => US [patent_app_date] => 2000-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3143 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255134.pdf [firstpage_image] =>[orig_patent_app_number] => 558006 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558006
Method for making high-frame-rate CCD imaging devices from otherwise ordinary and inexpensive CCD devices Apr 23, 2000 Issued
Array ( [id] => 4366910 [patent_doc_number] => 06274496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Method for single chamber processing of PECVD-Ti and CVD-TiN films for integrated contact/barrier applications in IC manufacturing' [patent_app_type] => 1 [patent_app_number] => 9/553833 [patent_app_country] => US [patent_app_date] => 2000-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4818 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274496.pdf [firstpage_image] =>[orig_patent_app_number] => 553833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/553833
Method for single chamber processing of PECVD-Ti and CVD-TiN films for integrated contact/barrier applications in IC manufacturing Apr 20, 2000 Issued
Array ( [id] => 1527095 [patent_doc_number] => 06478883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Silicon single crystal wafer, epitaxial silicon wafer, and methods for producing them' [patent_app_type] => B1 [patent_app_number] => 09/529661 [patent_app_country] => US [patent_app_date] => 2000-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 11537 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/478/06478883.pdf [firstpage_image] =>[orig_patent_app_number] => 09529661 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/529661
Silicon single crystal wafer, epitaxial silicon wafer, and methods for producing them Apr 17, 2000 Issued
Array ( [id] => 1505517 [patent_doc_number] => 06465892 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Interconnect structure for stacked semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/548916 [patent_app_country] => US [patent_app_date] => 2000-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 26 [patent_no_of_words] => 7282 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465892.pdf [firstpage_image] =>[orig_patent_app_number] => 09548916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/548916
Interconnect structure for stacked semiconductor device Apr 12, 2000 Issued
Array ( [id] => 1585288 [patent_doc_number] => 06358763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Methods of forming a mask pattern and methods of forming a field emitter tip mask' [patent_app_type] => B1 [patent_app_number] => 09/545978 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 4339 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/358/06358763.pdf [firstpage_image] =>[orig_patent_app_number] => 09545978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/545978
Methods of forming a mask pattern and methods of forming a field emitter tip mask Apr 9, 2000 Issued
09/546115 Selective absorption process for forming an activated doped region in a semiconductor Apr 9, 2000 Abandoned
Array ( [id] => 1466784 [patent_doc_number] => 06351841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method and apparatus for creating multi-gate transistors with integrated circuit polygon compactors' [patent_app_type] => B1 [patent_app_number] => 09/531725 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2114 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351841.pdf [firstpage_image] =>[orig_patent_app_number] => 09531725 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531725
Method and apparatus for creating multi-gate transistors with integrated circuit polygon compactors Mar 20, 2000 Issued
Array ( [id] => 1503643 [patent_doc_number] => 06465342 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => B1 [patent_app_number] => 09/524287 [patent_app_country] => US [patent_app_date] => 2000-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 35 [patent_no_of_words] => 13833 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465342.pdf [firstpage_image] =>[orig_patent_app_number] => 09524287 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/524287
Semiconductor device and its manufacturing method Mar 12, 2000 Issued
Array ( [id] => 4322129 [patent_doc_number] => 06331486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy' [patent_app_type] => 1 [patent_app_number] => 9/519897 [patent_app_country] => US [patent_app_date] => 2000-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 4177 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/331/06331486.pdf [firstpage_image] =>[orig_patent_app_number] => 519897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/519897
Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloy Mar 5, 2000 Issued
09/507335 Method of manufacturing a semiconductor device and a process of a thin film transistor Feb 17, 2000 Abandoned
Array ( [id] => 4291437 [patent_doc_number] => 06180421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Method and apparatus for manufacturing magnetic head' [patent_app_type] => 1 [patent_app_number] => 9/507555 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 50 [patent_no_of_words] => 8884 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180421.pdf [firstpage_image] =>[orig_patent_app_number] => 507555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507555
Method and apparatus for manufacturing magnetic head Feb 17, 2000 Issued
Array ( [id] => 4351375 [patent_doc_number] => 06291365 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Method for manufacturing thin gate silicon oxide layer' [patent_app_type] => 1 [patent_app_number] => 9/501957 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3808 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291365.pdf [firstpage_image] =>[orig_patent_app_number] => 501957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501957
Method for manufacturing thin gate silicon oxide layer Feb 9, 2000 Issued
Array ( [id] => 1395266 [patent_doc_number] => 06541400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Process for CVD deposition of fluorinated silicon glass layer on semiconductor wafer' [patent_app_type] => B1 [patent_app_number] => 09/501347 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3643 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/541/06541400.pdf [firstpage_image] =>[orig_patent_app_number] => 09501347 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501347
Process for CVD deposition of fluorinated silicon glass layer on semiconductor wafer Feb 8, 2000 Issued
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