Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4083734 [patent_doc_number] => 06162675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of preventing misalignment of selective silicide layer in the manufacture of a DRAM device and the DRAM device formed thereby' [patent_app_type] => 1 [patent_app_number] => 9/497405 [patent_app_country] => US [patent_app_date] => 2000-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 8530 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162675.pdf [firstpage_image] =>[orig_patent_app_number] => 497405 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497405
Method of preventing misalignment of selective silicide layer in the manufacture of a DRAM device and the DRAM device formed thereby Feb 2, 2000 Issued
Array ( [id] => 4341173 [patent_doc_number] => 06320740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Method for manufacturing a polarized electrode for an electric double-layer capacitor' [patent_app_type] => 1 [patent_app_number] => 9/496375 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5496 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320740.pdf [firstpage_image] =>[orig_patent_app_number] => 496375 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/496375
Method for manufacturing a polarized electrode for an electric double-layer capacitor Feb 1, 2000 Issued
Array ( [id] => 4246438 [patent_doc_number] => 06221686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of making a semiconductor image sensor' [patent_app_type] => 1 [patent_app_number] => 9/493366 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2542 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221686.pdf [firstpage_image] =>[orig_patent_app_number] => 493366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/493366
Method of making a semiconductor image sensor Jan 27, 2000 Issued
Array ( [id] => 6290285 [patent_doc_number] => 20020055190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-09 [patent_title] => 'Magnetic memory with structures that prevent disruptions to magnetization in sense layer' [patent_app_type] => new [patent_app_number] => 09/492557 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3107 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20020055190.pdf [firstpage_image] =>[orig_patent_app_number] => 09492557 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492557
Magnetic memory with structures that prevent disruptions to magnetization in sense layer Jan 26, 2000 Abandoned
Array ( [id] => 4294054 [patent_doc_number] => 06184094 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Method for producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/492366 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 42 [patent_no_of_words] => 6996 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184094.pdf [firstpage_image] =>[orig_patent_app_number] => 492366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492366
Method for producing semiconductor device Jan 26, 2000 Issued
Array ( [id] => 4353483 [patent_doc_number] => 06218226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method of forming an ESD protection device' [patent_app_type] => 1 [patent_app_number] => 9/488786 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3933 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218226.pdf [firstpage_image] =>[orig_patent_app_number] => 488786 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488786
Method of forming an ESD protection device Jan 20, 2000 Issued
Array ( [id] => 4087459 [patent_doc_number] => 06133132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method for controlling transistor spacer width' [patent_app_type] => 1 [patent_app_number] => 9/488605 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2837 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133132.pdf [firstpage_image] =>[orig_patent_app_number] => 488605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488605
Method for controlling transistor spacer width Jan 19, 2000 Issued
Array ( [id] => 4084231 [patent_doc_number] => 06162709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Use of an asymmetric waveform to control ion bombardment during substrate processing' [patent_app_type] => 1 [patent_app_number] => 9/481985 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 14499 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162709.pdf [firstpage_image] =>[orig_patent_app_number] => 481985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481985
Use of an asymmetric waveform to control ion bombardment during substrate processing Jan 10, 2000 Issued
Array ( [id] => 6882714 [patent_doc_number] => 20010049186 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'METHOD FOR ESTABLISHING ULTRA-THIN GATE INSULATOR USING ANNEAL IN AMMONIA' [patent_app_type] => new [patent_app_number] => 09/479506 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1313 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20010049186.pdf [firstpage_image] =>[orig_patent_app_number] => 09479506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/479506
Method for establishing ultra-thin gate insulator using anneal in ammonia Jan 6, 2000 Issued
Array ( [id] => 1390514 [patent_doc_number] => 06544875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Chemical vapor deposition of silicate high dielectric constant materials' [patent_app_type] => B1 [patent_app_number] => 09/478845 [patent_app_country] => US [patent_app_date] => 2000-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2759 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544875.pdf [firstpage_image] =>[orig_patent_app_number] => 09478845 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/478845
Chemical vapor deposition of silicate high dielectric constant materials Jan 6, 2000 Issued
Array ( [id] => 4266482 [patent_doc_number] => 06306691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Body driven SOI-MOS field effect transistor and method of forming the same' [patent_app_type] => 1 [patent_app_number] => 9/470505 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 52 [patent_no_of_words] => 21917 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306691.pdf [firstpage_image] =>[orig_patent_app_number] => 470505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/470505
Body driven SOI-MOS field effect transistor and method of forming the same Dec 21, 1999 Issued
Array ( [id] => 1418767 [patent_doc_number] => 06514879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-04 [patent_title] => 'Method and apparatus for dry/catalytic-wet steam oxidation of silicon' [patent_app_type] => B2 [patent_app_number] => 09/466235 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3660 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/514/06514879.pdf [firstpage_image] =>[orig_patent_app_number] => 09466235 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466235
Method and apparatus for dry/catalytic-wet steam oxidation of silicon Dec 16, 1999 Issued
Array ( [id] => 4408852 [patent_doc_number] => 06300245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Inductively coupled plasma powder vaporization for fabricating integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/460265 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2742 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300245.pdf [firstpage_image] =>[orig_patent_app_number] => 460265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/460265
Inductively coupled plasma powder vaporization for fabricating integrated circuits Dec 12, 1999 Issued
Array ( [id] => 4154021 [patent_doc_number] => 06103564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method for forming a diode in a surface layer of an SOI substrate' [patent_app_type] => 1 [patent_app_number] => 9/459336 [patent_app_country] => US [patent_app_date] => 1999-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 41 [patent_no_of_words] => 7190 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103564.pdf [firstpage_image] =>[orig_patent_app_number] => 459336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/459336
Method for forming a diode in a surface layer of an SOI substrate Dec 12, 1999 Issued
Array ( [id] => 4235728 [patent_doc_number] => 06165883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Method for forming multilayer sidewalls on a polymetal stack gate electrode' [patent_app_type] => 1 [patent_app_number] => 9/442456 [patent_app_country] => US [patent_app_date] => 1999-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 18 [patent_no_of_words] => 4815 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165883.pdf [firstpage_image] =>[orig_patent_app_number] => 442456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/442456
Method for forming multilayer sidewalls on a polymetal stack gate electrode Nov 17, 1999 Issued
09/437135 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME Nov 9, 1999 Abandoned
Array ( [id] => 6141822 [patent_doc_number] => 20020001935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'METHOD OF FORMING GATE ELECTRODE IN SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/434755 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2497 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20020001935.pdf [firstpage_image] =>[orig_patent_app_number] => 09434755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434755
METHOD OF FORMING GATE ELECTRODE IN SEMICONDUCTOR DEVICE Nov 4, 1999 Abandoned
09/428506 METHOD AND APPARATUS FOR FORMING AN OXIDIZED STRUCTURE ON A MICROELECTRONIC WORKPIECE Oct 26, 1999 Abandoned
Array ( [id] => 1467024 [patent_doc_number] => 06458677 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Process for fabricating an ONO structure' [patent_app_type] => B1 [patent_app_number] => 09/433186 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3595 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458677.pdf [firstpage_image] =>[orig_patent_app_number] => 09433186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433186
Process for fabricating an ONO structure Oct 24, 1999 Issued
Array ( [id] => 4246382 [patent_doc_number] => 06136688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'High stress oxide to eliminate BPSG/SiN cracking' [patent_app_type] => 1 [patent_app_number] => 9/421508 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1937 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136688.pdf [firstpage_image] =>[orig_patent_app_number] => 421508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421508
High stress oxide to eliminate BPSG/SiN cracking Oct 19, 1999 Issued
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