Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1507473 [patent_doc_number] => 06440849 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Microstructure control of copper interconnects' [patent_app_type] => B1 [patent_app_number] => 09/419986 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1356 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/440/06440849.pdf [firstpage_image] =>[orig_patent_app_number] => 09419986 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419986
Microstructure control of copper interconnects Oct 17, 1999 Issued
Array ( [id] => 1542568 [patent_doc_number] => 06372581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Process for nitriding the gate oxide layer of a semiconductor device and device obtained' [patent_app_type] => B1 [patent_app_number] => 09/403356 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 1455 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/372/06372581.pdf [firstpage_image] =>[orig_patent_app_number] => 09403356 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/403356
Process for nitriding the gate oxide layer of a semiconductor device and device obtained Oct 17, 1999 Issued
Array ( [id] => 1543731 [patent_doc_number] => 06397775 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Deposited film forming system and process' [patent_app_type] => B1 [patent_app_number] => 09/419115 [patent_app_country] => US [patent_app_date] => 1999-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 12108 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397775.pdf [firstpage_image] =>[orig_patent_app_number] => 09419115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419115
Deposited film forming system and process Oct 14, 1999 Issued
Array ( [id] => 1602640 [patent_doc_number] => 06432819 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method and apparatus of forming a sputtered doped seed layer' [patent_app_type] => B1 [patent_app_number] => 09/406325 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3535 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/432/06432819.pdf [firstpage_image] =>[orig_patent_app_number] => 09406325 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406325
Method and apparatus of forming a sputtered doped seed layer Sep 26, 1999 Issued
Array ( [id] => 4369055 [patent_doc_number] => 06287941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Surface finishing of SOI substrates using an EPI process' [patent_app_type] => 1 [patent_app_number] => 9/399985 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5733 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287941.pdf [firstpage_image] =>[orig_patent_app_number] => 399985 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399985
Surface finishing of SOI substrates using an EPI process Sep 19, 1999 Issued
Array ( [id] => 4183699 [patent_doc_number] => 06159845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method for manufacturing dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/395906 [patent_app_country] => US [patent_app_date] => 1999-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2218 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/159/06159845.pdf [firstpage_image] =>[orig_patent_app_number] => 395906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/395906
Method for manufacturing dielectric layer Sep 10, 1999 Issued
Array ( [id] => 4354321 [patent_doc_number] => 06218285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method for forming inter-metal dielectric layers in metallization process' [patent_app_type] => 1 [patent_app_number] => 9/387506 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2781 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218285.pdf [firstpage_image] =>[orig_patent_app_number] => 387506 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387506
Method for forming inter-metal dielectric layers in metallization process Aug 31, 1999 Issued
Array ( [id] => 1566113 [patent_doc_number] => 06376381 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Planarizing solutions, planarizing machines, and methods for mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies' [patent_app_type] => B1 [patent_app_number] => 09/387306 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3654 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376381.pdf [firstpage_image] =>[orig_patent_app_number] => 09387306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387306
Planarizing solutions, planarizing machines, and methods for mechanical and/or chemical-mechanical planarization of microelectronic substrate assemblies Aug 30, 1999 Issued
Array ( [id] => 7643589 [patent_doc_number] => 06429452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process' [patent_app_type] => B1 [patent_app_number] => 09/375455 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3461 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429452.pdf [firstpage_image] =>[orig_patent_app_number] => 09375455 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375455
Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process Aug 16, 1999 Issued
09/373245 NOVEL METHOD FOR IMPROVING FACETING EFFECT IN DUAL DAMASCENE PROCESS Aug 11, 1999 Abandoned
Array ( [id] => 4301882 [patent_doc_number] => 06251732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Method and apparatus for forming self-aligned code structures for semi conductor devices' [patent_app_type] => 1 [patent_app_number] => 9/371255 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3631 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251732.pdf [firstpage_image] =>[orig_patent_app_number] => 371255 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/371255
Method and apparatus for forming self-aligned code structures for semi conductor devices Aug 9, 1999 Issued
Array ( [id] => 6896197 [patent_doc_number] => 20010026987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-04 [patent_title] => 'METHOD FOR FORMING A CAPACITOR COMPATIBLE WITH HIGH DIELECTRIC CONSTANT MATERIALS HAVING TWO INDEPENDENT INSULATIVE LAYERS' [patent_app_type] => new [patent_app_number] => 09/357634 [patent_app_country] => US [patent_app_date] => 1999-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 4911 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20010026987.pdf [firstpage_image] =>[orig_patent_app_number] => 09357634 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357634
Method for forming a capacitor compatible with high dielectric constant materials having two independent insulative layers Jul 19, 1999 Issued
Array ( [id] => 1193052 [patent_doc_number] => 06730613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method for reducing by-product deposition in wafer processing equipment' [patent_app_type] => B1 [patent_app_number] => 09/354459 [patent_app_country] => US [patent_app_date] => 1999-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2625 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730613.pdf [firstpage_image] =>[orig_patent_app_number] => 09354459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/354459
Method for reducing by-product deposition in wafer processing equipment Jul 14, 1999 Issued
09/294487 LOW TEMPERATURE PLASMA-ENHANCED FORMATION OF INTEGRATED CIRCUITS Apr 19, 1999 Abandoned
Array ( [id] => 4395747 [patent_doc_number] => 06297171 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride' [patent_app_type] => 1 [patent_app_number] => 9/295642 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2138 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297171.pdf [firstpage_image] =>[orig_patent_app_number] => 295642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/295642
Semiconductor processing method of promoting photoresist adhesion to an outer substrate layer predominately comprising silicon nitride Apr 19, 1999 Issued
Array ( [id] => 1494922 [patent_doc_number] => 06403441 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method for fabricating storage capacitor using high dielectric constant material' [patent_app_type] => B1 [patent_app_number] => 09/291306 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 31 [patent_no_of_words] => 9910 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403441.pdf [firstpage_image] =>[orig_patent_app_number] => 09291306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/291306
Method for fabricating storage capacitor using high dielectric constant material Apr 14, 1999 Issued
Array ( [id] => 4380739 [patent_doc_number] => 06294397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment' [patent_app_type] => 1 [patent_app_number] => 9/262574 [patent_app_country] => US [patent_app_date] => 1999-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7144 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294397.pdf [firstpage_image] =>[orig_patent_app_number] => 262574 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/262574
Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment Mar 3, 1999 Issued
Array ( [id] => 4406565 [patent_doc_number] => 06171976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of chemical-mechanical polishing' [patent_app_type] => 1 [patent_app_number] => 9/261098 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 1461 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171976.pdf [firstpage_image] =>[orig_patent_app_number] => 261098 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261098
Method of chemical-mechanical polishing Mar 1, 1999 Issued
Array ( [id] => 7078506 [patent_doc_number] => 20010041401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'OPEN PATTERN INDUCTOR' [patent_app_type] => new [patent_app_number] => 09/261595 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3858 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 30 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20010041401.pdf [firstpage_image] =>[orig_patent_app_number] => 09261595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261595
Open pattern inductor Feb 25, 1999 Issued
Array ( [id] => 7078506 [patent_doc_number] => 20010041401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'OPEN PATTERN INDUCTOR' [patent_app_type] => new [patent_app_number] => 09/261595 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3858 [patent_no_of_claims] => 61 [patent_no_of_ind_claims] => 30 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20010041401.pdf [firstpage_image] =>[orig_patent_app_number] => 09261595 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261595
Open pattern inductor Feb 25, 1999 Issued
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