
Charles E. Cooley
Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )
| Most Active Art Unit | 1774 |
| Art Unit(s) | 1797, 1754, 3405, 2402, 1774, 1723 |
| Total Applications | 4068 |
| Issued Applications | 3145 |
| Pending Applications | 298 |
| Abandoned Applications | 660 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7078506
[patent_doc_number] => 20010041401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'OPEN PATTERN INDUCTOR'
[patent_app_type] => new
[patent_app_number] => 09/261595
[patent_app_country] => US
[patent_app_date] => 1999-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3858
[patent_no_of_claims] => 61
[patent_no_of_ind_claims] => 30
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20010041401.pdf
[firstpage_image] =>[orig_patent_app_number] => 09261595
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/261595 | Open pattern inductor | Feb 25, 1999 | Issued |
Array
(
[id] => 7078506
[patent_doc_number] => 20010041401
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-15
[patent_title] => 'OPEN PATTERN INDUCTOR'
[patent_app_type] => new
[patent_app_number] => 09/261595
[patent_app_country] => US
[patent_app_date] => 1999-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3858
[patent_no_of_claims] => 61
[patent_no_of_ind_claims] => 30
[patent_words_short_claim] => 34
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0041/20010041401.pdf
[firstpage_image] =>[orig_patent_app_number] => 09261595
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/261595 | Open pattern inductor | Feb 25, 1999 | Issued |
Array
(
[id] => 6615971
[patent_doc_number] => 20020016019
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-02-07
[patent_title] => 'PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE PACKAGE AND ORGANOPOLYSILOXANE COMPOSITION USED THEREFOR'
[patent_app_type] => new
[patent_app_number] => 09/256995
[patent_app_country] => US
[patent_app_date] => 1999-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 5123
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0016/20020016019.pdf
[firstpage_image] =>[orig_patent_app_number] => 09256995
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/256995 | PROCESS FOR PRODUCING SEMICONDUCTOR DEVICE PACKAGE AND ORGANOPOLYSILOXANE COMPOSITION USED THEREFOR | Feb 24, 1999 | Abandoned |
Array
(
[id] => 4407537
[patent_doc_number] => 06239013
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-05-29
[patent_title] => 'Method for transferring particles from an adhesive sheet to a substrate'
[patent_app_type] => 1
[patent_app_number] => 9/253655
[patent_app_country] => US
[patent_app_date] => 1999-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 4244
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/239/06239013.pdf
[firstpage_image] =>[orig_patent_app_number] => 253655
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/253655 | Method for transferring particles from an adhesive sheet to a substrate | Feb 18, 1999 | Issued |
Array
(
[id] => 4354278
[patent_doc_number] => 06218282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-17
[patent_title] => 'Method of forming low dielectric tungsten lined interconnection system'
[patent_app_type] => 1
[patent_app_number] => 9/252184
[patent_app_country] => US
[patent_app_date] => 1999-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2840
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/218/06218282.pdf
[firstpage_image] =>[orig_patent_app_number] => 252184
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/252184 | Method of forming low dielectric tungsten lined interconnection system | Feb 17, 1999 | Issued |
Array
(
[id] => 4235071
[patent_doc_number] => 06143580
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-07
[patent_title] => 'Methods of forming a mask pattern and methods of forming a field emitter tip mask'
[patent_app_type] => 1
[patent_app_number] => 9/251176
[patent_app_country] => US
[patent_app_date] => 1999-02-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 4229
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/143/06143580.pdf
[firstpage_image] =>[orig_patent_app_number] => 251176
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/251176 | Methods of forming a mask pattern and methods of forming a field emitter tip mask | Feb 16, 1999 | Issued |
Array
(
[id] => 1149549
[patent_doc_number] => 06770555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-03
[patent_title] => 'Process for fabricating semiconductor integrated circuit device having polycide line and impurity region respectively exposed to contact holes different in depth'
[patent_app_type] => B2
[patent_app_number] => 09/247926
[patent_app_country] => US
[patent_app_date] => 1999-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5100
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/770/06770555.pdf
[firstpage_image] =>[orig_patent_app_number] => 09247926
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/247926 | Process for fabricating semiconductor integrated circuit device having polycide line and impurity region respectively exposed to contact holes different in depth | Feb 10, 1999 | Issued |
Array
(
[id] => 4215328
[patent_doc_number] => 06110843
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Etch back method for smoothing microbubble-generated defects in spin-on-glass interlayer dielectric'
[patent_app_type] => 1
[patent_app_number] => 9/246296
[patent_app_country] => US
[patent_app_date] => 1999-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 3107
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/110/06110843.pdf
[firstpage_image] =>[orig_patent_app_number] => 246296
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/246296 | Etch back method for smoothing microbubble-generated defects in spin-on-glass interlayer dielectric | Feb 7, 1999 | Issued |
Array
(
[id] => 4319027
[patent_doc_number] => 06248658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-19
[patent_title] => 'Method of forming submicron-dimensioned metal patterns'
[patent_app_type] => 1
[patent_app_number] => 9/229264
[patent_app_country] => US
[patent_app_date] => 1999-01-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5184
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/248/06248658.pdf
[firstpage_image] =>[orig_patent_app_number] => 229264
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/229264 | Method of forming submicron-dimensioned metal patterns | Jan 12, 1999 | Issued |
Array
(
[id] => 6896224
[patent_doc_number] => 20010027014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-10-04
[patent_title] => 'METHOD OF FABRICATING INTERCONNECT'
[patent_app_type] => new
[patent_app_number] => 09/228435
[patent_app_country] => US
[patent_app_date] => 1999-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1930
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0027/20010027014.pdf
[firstpage_image] =>[orig_patent_app_number] => 09228435
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/228435 | METHOD OF FABRICATING INTERCONNECT | Jan 10, 1999 | Abandoned |
Array
(
[id] => 4369427
[patent_doc_number] => 06287968
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-09-11
[patent_title] => 'Method of defining copper seed layer for selective electroless plating processing'
[patent_app_type] => 1
[patent_app_number] => 9/225175
[patent_app_country] => US
[patent_app_date] => 1999-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 14
[patent_no_of_words] => 4318
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/287/06287968.pdf
[firstpage_image] =>[orig_patent_app_number] => 225175
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/225175 | Method of defining copper seed layer for selective electroless plating processing | Jan 3, 1999 | Issued |
Array
(
[id] => 4302009
[patent_doc_number] => 06251741
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Method of manufacturing a semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/219786
[patent_app_country] => US
[patent_app_date] => 1998-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3084
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/251/06251741.pdf
[firstpage_image] =>[orig_patent_app_number] => 219786
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/219786 | Method of manufacturing a semiconductor device | Dec 22, 1998 | Issued |
Array
(
[id] => 4406643
[patent_doc_number] => 06171982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same'
[patent_app_type] => 1
[patent_app_number] => 9/218416
[patent_app_country] => US
[patent_app_date] => 1998-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 30
[patent_no_of_words] => 22229
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 66
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/171/06171982.pdf
[firstpage_image] =>[orig_patent_app_number] => 218416
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/218416 | Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same | Dec 21, 1998 | Issued |
Array
(
[id] => 1458946
[patent_doc_number] => 06426308
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-30
[patent_title] => 'Methods for forming films having high dielectric constants'
[patent_app_type] => B1
[patent_app_number] => 09/209196
[patent_app_country] => US
[patent_app_date] => 1998-12-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4136
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 249
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/426/06426308.pdf
[firstpage_image] =>[orig_patent_app_number] => 09209196
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/209196 | Methods for forming films having high dielectric constants | Dec 9, 1998 | Issued |
Array
(
[id] => 4356577
[patent_doc_number] => 06174743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-16
[patent_title] => 'Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines'
[patent_app_type] => 1
[patent_app_number] => 9/208623
[patent_app_country] => US
[patent_app_date] => 1998-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 6529
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 813
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/174/06174743.pdf
[firstpage_image] =>[orig_patent_app_number] => 208623
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208623 | Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines | Dec 7, 1998 | Issued |
Array
(
[id] => 4247993
[patent_doc_number] => 06221794
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines'
[patent_app_type] => 1
[patent_app_number] => 9/208596
[patent_app_country] => US
[patent_app_date] => 1998-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 5815
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 393
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/221/06221794.pdf
[firstpage_image] =>[orig_patent_app_number] => 208596
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/208596 | Method of reducing incidence of stress-induced voiding in semiconductor interconnect lines | Dec 7, 1998 | Issued |
Array
(
[id] => 4156394
[patent_doc_number] => 06156654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices'
[patent_app_type] => 1
[patent_app_number] => 9/206746
[patent_app_country] => US
[patent_app_date] => 1998-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 20
[patent_no_of_words] => 4074
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 298
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156654.pdf
[firstpage_image] =>[orig_patent_app_number] => 206746
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/206746 | Pulsed laser salicidation for fabrication of ultra-thin silicides in sub-quarter micron devices | Dec 6, 1998 | Issued |
Array
(
[id] => 1600500
[patent_doc_number] => 06475904
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2002-11-05
[patent_title] => 'Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques'
[patent_app_type] => B2
[patent_app_number] => 09/204166
[patent_app_country] => US
[patent_app_date] => 1998-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 28
[patent_no_of_words] => 5107
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/475/06475904.pdf
[firstpage_image] =>[orig_patent_app_number] => 09204166
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/204166 | Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques | Dec 2, 1998 | Issued |
Array
(
[id] => 6961400
[patent_doc_number] => 20010012692
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-08-09
[patent_title] => 'THICK-FILM ETCH-BACK PROCESS FOR USE IN MANUFACTURING FINE-LINE HYBRID CIRCUITS'
[patent_app_type] => new
[patent_app_number] => 09/204405
[patent_app_country] => US
[patent_app_date] => 1998-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2499
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0012/20010012692.pdf
[firstpage_image] =>[orig_patent_app_number] => 09204405
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/204405 | THICK-FILM ETCH-BACK PROCESS FOR USE IN MANUFACTURING FINE-LINE HYBRID CIRCUITS | Dec 1, 1998 | Abandoned |
Array
(
[id] => 4156451
[patent_doc_number] => 06156658
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Ultra-thin resist and silicon/oxide hard mask for metal etch'
[patent_app_type] => 1
[patent_app_number] => 9/203774
[patent_app_country] => US
[patent_app_date] => 1998-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 5209
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/156/06156658.pdf
[firstpage_image] =>[orig_patent_app_number] => 203774
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/203774 | Ultra-thin resist and silicon/oxide hard mask for metal etch | Dec 1, 1998 | Issued |