Charles E. Cooley

Array ( [id] => 4408675 [patent_doc_number] => 06265308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Slotted damascene lines for low resistive wiring lines for integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/201205 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 4777 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265308.pdf [firstpage_image] =>[orig_patent_app_number] => 201205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1433352 [patent_doc_number] => 06340642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity' [patent_app_type] => B1 [patent_app_number] => 09/201899 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2485 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340642.pdf [firstpage_image] =>[orig_patent_app_number] => 09201899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1285139 [patent_doc_number] => 06638829 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-28 [patent_title] => 'Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture' [patent_app_type] => B1 [patent_app_number] => 09/199960 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2962 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/638/06638829.pdf [firstpage_image] =>[orig_patent_app_number] => 09199960 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4251010 [patent_doc_number] => 06207591 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method and equipment for manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/190444 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 12544 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207591.pdf [firstpage_image] =>[orig_patent_app_number] => 190444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4247390 [patent_doc_number] => 06221752 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method of mending erosion of bonding pad' [patent_app_type] => 1 [patent_app_number] => 9/186744 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1619 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/221/06221752.pdf [firstpage_image] =>[orig_patent_app_number] => 186744 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466883 [patent_doc_number] => 06458613 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Method for manufacturing a liquid crystal display using a selective etching method' [patent_app_type] => B1 [patent_app_number] => 09/184825 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 3750 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/458/06458613.pdf [firstpage_image] =>[orig_patent_app_number] => 09184825 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4124681 [patent_doc_number] => 06127215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Deep pivot mask for enhanced buried-channel PFET performance and reliability' [patent_app_type] => 1 [patent_app_number] => 9/181964 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 3318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127215.pdf [firstpage_image] =>[orig_patent_app_number] => 181964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4245865 [patent_doc_number] => 06136656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method to create a depleted poly MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/176815 [patent_app_country] => US [patent_app_date] => 1998-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2446 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136656.pdf [firstpage_image] =>[orig_patent_app_number] => 176815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6947932 [patent_doc_number] => 20010021566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'ANODIC OXIDIZATION METHODS' [patent_app_type] => new [patent_app_number] => 09/175844 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3977 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20010021566.pdf [firstpage_image] =>[orig_patent_app_number] => 09175844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302050 [patent_doc_number] => 06187600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Silicon substrate evaluation method and semiconductor device manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/175404 [patent_app_country] => US [patent_app_date] => 1998-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3436 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187600.pdf [firstpage_image] =>[orig_patent_app_number] => 175404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1101744 [patent_doc_number] => 06815336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing' [patent_app_type] => B1 [patent_app_number] => 09/160965 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 2523 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815336.pdf [firstpage_image] =>[orig_patent_app_number] => 09160965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155890 [patent_doc_number] => 06114257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Process for modified oxidation of a semiconductor substrate using chlorine plasma' [patent_app_type] => 1 [patent_app_number] => 9/153986 [patent_app_country] => US [patent_app_date] => 1998-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3070 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114257.pdf [firstpage_image] =>[orig_patent_app_number] => 153986 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302805 [patent_doc_number] => 06187652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method of fabrication of multiple-layer high density substrate' [patent_app_type] => 1 [patent_app_number] => 9/152365 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1974 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187652.pdf [firstpage_image] =>[orig_patent_app_number] => 152365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4125238 [patent_doc_number] => 06127251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Semiconductor device with a reduced width gate dielectric and method of making same' [patent_app_type] => 1 [patent_app_number] => 9/149398 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3798 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127251.pdf [firstpage_image] =>[orig_patent_app_number] => 149398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4178541 [patent_doc_number] => 06037275 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Nanoporous silica via combined stream deposition' [patent_app_type] => 1 [patent_app_number] => 9/140855 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8402 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/037/06037275.pdf [firstpage_image] =>[orig_patent_app_number] => 140855 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1478260 [patent_doc_number] => 06451714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-09-17 [patent_title] => 'System and method for selectively increasing surface temperature of an object' [patent_app_type] => B2 [patent_app_number] => 09/139934 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4670 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451714.pdf [firstpage_image] =>[orig_patent_app_number] => 09139934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4214942 [patent_doc_number] => 06087200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Using microspheres as a stress buffer for integrated circuit prototypes' [patent_app_type] => 1 [patent_app_number] => 9/133205 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2800 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087200.pdf [firstpage_image] =>[orig_patent_app_number] => 133205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417123 [patent_doc_number] => 06194270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Process for the manufacturing of an electrically programmable non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 9/130720 [patent_app_country] => US [patent_app_date] => 1998-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 2221 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194270.pdf [firstpage_image] =>[orig_patent_app_number] => 130720 [rel_patent_id] =>[rel_patent_doc_number] =>)