Search

Charles E. Cooley

Examiner (ID: 18585, Phone: (571)272-1139 , Office: P/1774 )

Most Active Art Unit
1774
Art Unit(s)
1797, 1754, 3405, 2402, 1774, 1723
Total Applications
4068
Issued Applications
3145
Pending Applications
298
Abandoned Applications
660

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18346884 [patent_doc_number] => 20230134994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SYSTEMS AND METHODS FOR NITRIDIZATION OF NIOBIUM TRACES [patent_app_type] => utility [patent_app_number] => 17/517263 [patent_app_country] => US [patent_app_date] => 2021-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17517263 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/517263
SYSTEMS AND METHODS FOR NITRIDIZATION OF NIOBIUM TRACES Nov 1, 2021 Abandoned
Array ( [id] => 18346486 [patent_doc_number] => 20230134596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => METAL STACK TO IMPROVE STACK THERMAL STABILITY [patent_app_type] => utility [patent_app_number] => 17/514039 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4974 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/514039
METAL STACK TO IMPROVE STACK THERMAL STABILITY Oct 28, 2021 Abandoned
Array ( [id] => 17582921 [patent_doc_number] => 20220139776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH A LOW-RESISTIVITY METAL [patent_app_type] => utility [patent_app_number] => 17/507136 [patent_app_country] => US [patent_app_date] => 2021-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3311 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17507136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/507136
METHOD FOR FILLING RECESSED FEATURES IN SEMICONDUCTOR DEVICES WITH A LOW-RESISTIVITY METAL Oct 20, 2021 Abandoned
Array ( [id] => 18796894 [patent_doc_number] => 11830728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Methods for seamless gap filling of dielectric material [patent_app_type] => utility [patent_app_number] => 17/499955 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499955
Methods for seamless gap filling of dielectric material Oct 12, 2021 Issued
Array ( [id] => 17373678 [patent_doc_number] => 20220028730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/498071 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498071 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498071
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Oct 10, 2021 Abandoned
Array ( [id] => 18312540 [patent_doc_number] => 20230116440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => TOP VIA STRUCTURE MADE WITH BI-LAYER TEMPLATE [patent_app_type] => utility [patent_app_number] => 17/498718 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498718 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498718
TOP VIA STRUCTURE MADE WITH BI-LAYER TEMPLATE Oct 10, 2021 Pending
Array ( [id] => 18311311 [patent_doc_number] => 20230115211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => SELF-ASSEMBLED MONOLAYER FOR SELECTIVE DEPOSITION [patent_app_type] => utility [patent_app_number] => 17/498190 [patent_app_country] => US [patent_app_date] => 2021-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8775 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498190
Self-assembled monolayer for selective deposition Oct 10, 2021 Issued
Array ( [id] => 18417592 [patent_doc_number] => 11672151 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Display panel including display signal pads and sensing signal pads mounted on the display panel sidewall [patent_app_type] => utility [patent_app_number] => 17/493426 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5333 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493426 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493426
Display panel including display signal pads and sensing signal pads mounted on the display panel sidewall Oct 3, 2021 Issued
Array ( [id] => 17359949 [patent_doc_number] => 20220020745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/492687 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492687 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/492687
Semiconductor device Oct 3, 2021 Issued
Array ( [id] => 19221600 [patent_doc_number] => 20240186304 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => LIGHT-EMITTING SUBSTRATE, BACKLIGHT MODULE AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/795414 [patent_app_country] => US [patent_app_date] => 2021-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16115 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17795414 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/795414
Light-emitting substrate, backlight module and display device Sep 29, 2021 Issued
Array ( [id] => 19582532 [patent_doc_number] => 12148660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Low resistance and high reliability metallization module [patent_app_type] => utility [patent_app_number] => 17/487123 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 10076 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487123 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487123
Low resistance and high reliability metallization module Sep 27, 2021 Issued
Array ( [id] => 18279285 [patent_doc_number] => 20230094757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => TOP VIA PROCESS WITH DAMASCENE METAL [patent_app_type] => utility [patent_app_number] => 17/481362 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481362 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481362
Top via process with damascene metal Sep 21, 2021 Issued
Array ( [id] => 17551540 [patent_doc_number] => 20220122882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => SEMICONDUCTOR STRUCTURE MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/480365 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5437 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17480365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/480365
Semiconductor structure manufacturing method Sep 20, 2021 Issued
Array ( [id] => 17402870 [patent_doc_number] => 20220044961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/471256 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471256 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471256
Semiconductor structure and manufacturing method thereof Sep 9, 2021 Issued
Array ( [id] => 17993232 [patent_doc_number] => 20220359269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR FEATURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/471666 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8151 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471666
Semiconductor feature and method for manufacturing the same Sep 9, 2021 Issued
Array ( [id] => 18239649 [patent_doc_number] => 20230071960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => Compartment Shielding With Metal Frame and Cap [patent_app_type] => utility [patent_app_number] => 17/447041 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447041 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447041
Compartment shielding with metal frame and cap Sep 6, 2021 Issued
Array ( [id] => 18481173 [patent_doc_number] => 11694927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Formation method of semiconductor device with contact structures [patent_app_type] => utility [patent_app_number] => 17/464917 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 5294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464917
Formation method of semiconductor device with contact structures Sep 1, 2021 Issued
Array ( [id] => 17985981 [patent_doc_number] => 20220352018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/446215 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446215 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/446215
CARBON-BASED LINER TO REDUCE CONTACT RESISTANCE Aug 26, 2021 Pending
Array ( [id] => 18230060 [patent_doc_number] => 20230069054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY WITH MULTI-LAYER EPITAXY AND LAYER TRANSFER [patent_app_type] => utility [patent_app_number] => 17/410257 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15978 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410257 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410257
GALLIUM NITRIDE (GAN) INTEGRATED CIRCUIT TECHNOLOGY WITH MULTI-LAYER EPITAXY AND LAYER TRANSFER Aug 23, 2021 Abandoned
Array ( [id] => 18212567 [patent_doc_number] => 20230058831 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => MOLECULAR LAYER DEPOSITION LINER FOR 3D NAND [patent_app_type] => utility [patent_app_number] => 17/407533 [patent_app_country] => US [patent_app_date] => 2021-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7525 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/407533
MOLECULAR LAYER DEPOSITION LINER FOR 3D NAND Aug 19, 2021 Pending
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