Search

Charles E. Phillips

Examiner (ID: 298)

Most Active Art Unit
3751
Art Unit(s)
3751, 3105, 2403
Total Applications
2438
Issued Applications
1788
Pending Applications
61
Abandoned Applications
589

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17056550 [patent_doc_number] => 20210265984 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => TWO-TERMINAL PROTECTIVE DEVICE USING PARASITIC ENERGY HARVESTING [patent_app_type] => utility [patent_app_number] => 17/261792 [patent_app_country] => US [patent_app_date] => 2019-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261792 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/261792
Two-terminal protective device using parasitic energy harvesting Aug 13, 2019 Issued
Array ( [id] => 16565570 [patent_doc_number] => 10890938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Clock duty cycle adjustment and calibration circuit and method of operating same [patent_app_type] => utility [patent_app_number] => 16/539228 [patent_app_country] => US [patent_app_date] => 2019-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 21317 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16539228 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/539228
Clock duty cycle adjustment and calibration circuit and method of operating same Aug 12, 2019 Issued
Array ( [id] => 16149523 [patent_doc_number] => 10707849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Synchronous mirror delay circuit and synchronous mirror delay operation method [patent_app_type] => utility [patent_app_number] => 16/537011 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4875 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16537011 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/537011
Synchronous mirror delay circuit and synchronous mirror delay operation method Aug 8, 2019 Issued
Array ( [id] => 16610015 [patent_doc_number] => 10911040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => High power radio frequency switches with low leakage current and low insertion loss [patent_app_type] => utility [patent_app_number] => 16/532932 [patent_app_country] => US [patent_app_date] => 2019-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 7700 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16532932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/532932
High power radio frequency switches with low leakage current and low insertion loss Aug 5, 2019 Issued
Array ( [id] => 16418580 [patent_doc_number] => 10826490 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Switch circuit [patent_app_type] => utility [patent_app_number] => 16/529936 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5533 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 297 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16529936 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/529936
Switch circuit Aug 1, 2019 Issued
Array ( [id] => 17153169 [patent_doc_number] => 11146268 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => High voltage integrated circuit [patent_app_type] => utility [patent_app_number] => 16/528921 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6183 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 393 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528921
High voltage integrated circuit Jul 31, 2019 Issued
Array ( [id] => 16324788 [patent_doc_number] => 10784768 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Conversion circuit and conversion circuitry [patent_app_type] => utility [patent_app_number] => 16/528675 [patent_app_country] => US [patent_app_date] => 2019-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5742 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528675 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528675
Conversion circuit and conversion circuitry Jul 31, 2019 Issued
Array ( [id] => 16433567 [patent_doc_number] => 10833670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Semiconductor integrated circuit and adjustment method for semiconductor integrated circuit [patent_app_type] => utility [patent_app_number] => 16/527338 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16527338 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/527338
Semiconductor integrated circuit and adjustment method for semiconductor integrated circuit Jul 30, 2019 Issued
Array ( [id] => 16216854 [patent_doc_number] => 10732660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Measuring internal voltages of packaged electronic devices [patent_app_type] => utility [patent_app_number] => 16/526801 [patent_app_country] => US [patent_app_date] => 2019-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526801 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/526801
Measuring internal voltages of packaged electronic devices Jul 29, 2019 Issued
Array ( [id] => 17638725 [patent_doc_number] => 11349464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Waveform shaping circuit, signal generation apparatus, and signal reading system [patent_app_type] => utility [patent_app_number] => 17/262058 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 31679 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17262058 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/262058
Waveform shaping circuit, signal generation apparatus, and signal reading system Jul 23, 2019 Issued
Array ( [id] => 15734679 [patent_doc_number] => 10615781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => Semiconductor apparatus [patent_app_type] => utility [patent_app_number] => 16/517188 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4731 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517188 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517188
Semiconductor apparatus Jul 18, 2019 Issued
Array ( [id] => 15092569 [patent_doc_number] => 20190341096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => TECHNIQUES FOR CLOCK SIGNAL JITTER GENERATION [patent_app_type] => utility [patent_app_number] => 16/517230 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11369 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517230 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517230
Techniques for clock signal jitter generation Jul 18, 2019 Issued
Array ( [id] => 15045105 [patent_doc_number] => 20190333557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A CLOCK ADJUSTMENT CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/504640 [patent_app_country] => US [patent_app_date] => 2019-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8506 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16504640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/504640
Semiconductor device including a clock adjustment circuit Jul 7, 2019 Issued
Array ( [id] => 15806913 [patent_doc_number] => 20200126599 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => POWER NOISE REDUCTION TECHNIQUE FOR HIGH DENSITY MEMORY WITH GATING [patent_app_type] => utility [patent_app_number] => 16/503805 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3125 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503805 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503805
Power noise reduction technique for high density memory with gating Jul 4, 2019 Issued
Array ( [id] => 16265273 [patent_doc_number] => 10756724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => RF circuit with switch transistor with body connection [patent_app_type] => utility [patent_app_number] => 16/413785 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3981 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413785 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413785
RF circuit with switch transistor with body connection May 15, 2019 Issued
Array ( [id] => 16905740 [patent_doc_number] => 20210184656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => DUTY RATIO CORRECTION CIRCUIT AND SIGNAL GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/269840 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17269840 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/269840
Duty ratio correction circuit and signal generation circuit May 9, 2019 Issued
Array ( [id] => 16387109 [patent_doc_number] => 10811959 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-20 [patent_title] => Switched capacitor voltage converter and method for operating a switched capacitor voltage converter [patent_app_type] => utility [patent_app_number] => 16/409644 [patent_app_country] => US [patent_app_date] => 2019-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6736 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16409644 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/409644
Switched capacitor voltage converter and method for operating a switched capacitor voltage converter May 9, 2019 Issued
Array ( [id] => 15777411 [patent_doc_number] => 20200119723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-16 [patent_title] => LATCH CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/407757 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/407757
Latch circuit May 8, 2019 Issued
Array ( [id] => 16410760 [patent_doc_number] => 10819331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-10-27 [patent_title] => Self-regulating body-biasing techniques for process, voltage, and temperature (PVT) fluctuation compensation in fully-depleted silicon-on-insulator (FDSOI) semiconductors [patent_app_type] => utility [patent_app_number] => 16/404931 [patent_app_country] => US [patent_app_date] => 2019-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3947 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16404931 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/404931
Self-regulating body-biasing techniques for process, voltage, and temperature (PVT) fluctuation compensation in fully-depleted silicon-on-insulator (FDSOI) semiconductors May 6, 2019 Issued
Array ( [id] => 15219543 [patent_doc_number] => 20190372458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => ELEMENTARY CELL AND CHARGE PUMPS COMPRISING SUCH AN ELEMENTARY CELL [patent_app_type] => utility [patent_app_number] => 16/402905 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3949 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402905 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402905
Elementary cell and charge pumps comprising such an elementary cell May 2, 2019 Issued
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