Search

Charles E. Phillips

Examiner (ID: 298)

Most Active Art Unit
3751
Art Unit(s)
3751, 3105, 2403
Total Applications
2438
Issued Applications
1788
Pending Applications
61
Abandoned Applications
589

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14785991 [patent_doc_number] => 20190267893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => INTERNAL VOLTAGE GENERATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/283037 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283037 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283037
Internal voltage generation circuit Feb 21, 2019 Issued
Array ( [id] => 16309372 [patent_doc_number] => 10778188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-15 [patent_title] => Harmonic rejection filter with transimpedence amplifiers [patent_app_type] => utility [patent_app_number] => 16/283689 [patent_app_country] => US [patent_app_date] => 2019-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7535 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283689 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/283689
Harmonic rejection filter with transimpedence amplifiers Feb 21, 2019 Issued
Array ( [id] => 16257440 [patent_doc_number] => 20200266815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-20 [patent_title] => Controlled Active Resistance [patent_app_type] => utility [patent_app_number] => 16/276482 [patent_app_country] => US [patent_app_date] => 2019-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16276482 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/276482
Controlled active resistance Feb 13, 2019 Issued
Array ( [id] => 15235597 [patent_doc_number] => 10505532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Output buffer and operation method thereof [patent_app_type] => utility [patent_app_number] => 16/275304 [patent_app_country] => US [patent_app_date] => 2019-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5722 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16275304 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/275304
Output buffer and operation method thereof Feb 12, 2019 Issued
Array ( [id] => 16462490 [patent_doc_number] => 10845837 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Semiconductor device including non-volatile memory, a bias current generator and an on-chip termination resistor, method of fabricating the same and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/273104 [patent_app_country] => US [patent_app_date] => 2019-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 23 [patent_no_of_words] => 17160 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16273104 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/273104
Semiconductor device including non-volatile memory, a bias current generator and an on-chip termination resistor, method of fabricating the same and method of operating the same Feb 10, 2019 Issued
Array ( [id] => 14905943 [patent_doc_number] => 20190296737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => DIODE CIRCUIT FOR EFFICIENT OPERATION [patent_app_type] => utility [patent_app_number] => 16/263659 [patent_app_country] => US [patent_app_date] => 2019-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16263659 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/263659
DIODE CIRCUIT FOR EFFICIENT OPERATION Jan 30, 2019 Abandoned
Array ( [id] => 15707181 [patent_doc_number] => 10609792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Digital load control system providing power and communication via existing power wiring [patent_app_type] => utility [patent_app_number] => 16/256880 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 25086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256880
Digital load control system providing power and communication via existing power wiring Jan 23, 2019 Issued
Array ( [id] => 14754387 [patent_doc_number] => 20190260367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => POWER AMPLIFIER SATURATION DETECTION [patent_app_type] => utility [patent_app_number] => 16/256542 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4890 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256542 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256542
POWER AMPLIFIER SATURATION DETECTION Jan 23, 2019 Abandoned
Array ( [id] => 15761691 [patent_doc_number] => 10622983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Apparatus and method for comparing input current to set of current thresholds [patent_app_type] => utility [patent_app_number] => 16/251997 [patent_app_country] => US [patent_app_date] => 2019-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8934 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16251997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/251997
Apparatus and method for comparing input current to set of current thresholds Jan 17, 2019 Issued
Array ( [id] => 14871875 [patent_doc_number] => 20190286179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => Dynamic Adjustment of Operating Conditions of Integrated Circuits [patent_app_type] => utility [patent_app_number] => 16/250432 [patent_app_country] => US [patent_app_date] => 2019-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16250432 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/250432
Dynamic adjustment of operating conditions of integrated circuits Jan 16, 2019 Issued
Array ( [id] => 14589193 [patent_doc_number] => 20190222205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => VECTOR SUM CIRCUIT AND PHASE CONTROLLER USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/248159 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248159 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248159
Vector sum circuit and phase controller using the same Jan 14, 2019 Issued
Array ( [id] => 15761689 [patent_doc_number] => 10622982 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Measurement, calibration and tuning of memory bus duty cycle [patent_app_type] => utility [patent_app_number] => 16/244924 [patent_app_country] => US [patent_app_date] => 2019-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6913 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244924 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244924
Measurement, calibration and tuning of memory bus duty cycle Jan 9, 2019 Issued
Array ( [id] => 15201439 [patent_doc_number] => 10498231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Charge pump circuitry [patent_app_type] => utility [patent_app_number] => 16/244019 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 10726 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244019 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244019
Charge pump circuitry Jan 8, 2019 Issued
Array ( [id] => 14632675 [patent_doc_number] => 20190229710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => CLOCK DISTRIBUTION [patent_app_type] => utility [patent_app_number] => 16/244002 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16244002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/244002
Clock distribution Jan 8, 2019 Issued
Array ( [id] => 16234632 [patent_doc_number] => 10742201 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Hybrid pulse/master-slave data latch [patent_app_type] => utility [patent_app_number] => 16/243954 [patent_app_country] => US [patent_app_date] => 2019-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10739 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243954 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/243954
Hybrid pulse/master-slave data latch Jan 8, 2019 Issued
Array ( [id] => 14723801 [patent_doc_number] => 20190252964 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => CONVERSION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/234598 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16234598 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/234598
Conversion circuit Dec 27, 2018 Issued
Array ( [id] => 16774627 [patent_doc_number] => 10985753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-20 [patent_title] => Apparatuses and methods for providing bias signals in a semiconductor device [patent_app_type] => utility [patent_app_number] => 16/229266 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8991 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229266 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/229266
Apparatuses and methods for providing bias signals in a semiconductor device Dec 20, 2018 Issued
Array ( [id] => 16373021 [patent_doc_number] => 10804795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Method for synchronizing power charge-pump with system clock [patent_app_type] => utility [patent_app_number] => 16/227038 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4053 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227038 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227038
Method for synchronizing power charge-pump with system clock Dec 19, 2018 Issued
Array ( [id] => 17746198 [patent_doc_number] => 11394288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Negative voltage generation circuit and power conversion device using same [patent_app_type] => utility [patent_app_number] => 16/962015 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9024 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16962015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/962015
Negative voltage generation circuit and power conversion device using same Dec 10, 2018 Issued
Array ( [id] => 17048612 [patent_doc_number] => 11101807 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-24 [patent_title] => Phase-locked loop (PLL) circuit [patent_app_type] => utility [patent_app_number] => 16/216162 [patent_app_country] => US [patent_app_date] => 2018-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 9013 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16216162 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/216162
Phase-locked loop (PLL) circuit Dec 10, 2018 Issued
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