Search

Charles E. Phillips

Examiner (ID: 298)

Most Active Art Unit
3751
Art Unit(s)
3751, 3105, 2403
Total Applications
2438
Issued Applications
1788
Pending Applications
61
Abandoned Applications
589

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15612343 [patent_doc_number] => 10587246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Semiconductor circuit and method of operating the circuit [patent_app_type] => utility [patent_app_number] => 16/212193 [patent_app_country] => US [patent_app_date] => 2018-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 13740 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16212193 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/212193
Semiconductor circuit and method of operating the circuit Dec 5, 2018 Issued
Array ( [id] => 16724618 [patent_doc_number] => 20210091765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => POWER TRANSMISSION DEVICE AND CONTACTLESS POWER TRANSMISSION DEVICE [patent_app_type] => utility [patent_app_number] => 16/954518 [patent_app_country] => US [patent_app_date] => 2018-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16954518 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/954518
Power transmission device and contactless power transmission device Dec 2, 2018 Issued
Array ( [id] => 16049075 [patent_doc_number] => 10686428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Cell of transmission gate free circuit and integrated circuit layout including the same [patent_app_type] => utility [patent_app_number] => 16/204932 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 16216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204932 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204932
Cell of transmission gate free circuit and integrated circuit layout including the same Nov 28, 2018 Issued
Array ( [id] => 16433554 [patent_doc_number] => 10833657 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Variable output resistance in a playback path with closed-loop pulse-width modulation driver [patent_app_type] => utility [patent_app_number] => 16/181792 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4530 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181792 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181792
Variable output resistance in a playback path with closed-loop pulse-width modulation driver Nov 5, 2018 Issued
Array ( [id] => 15287449 [patent_doc_number] => 10516400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-24 [patent_title] => Phase-locked loop and delay-locked loop [patent_app_type] => utility [patent_app_number] => 16/181625 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 6891 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181625 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181625
Phase-locked loop and delay-locked loop Nov 5, 2018 Issued
Array ( [id] => 15674331 [patent_doc_number] => 10601410 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-24 [patent_title] => Offset cancellation of duty cycle detector [patent_app_type] => utility [patent_app_number] => 16/179349 [patent_app_country] => US [patent_app_date] => 2018-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9378 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16179349 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/179349
Offset cancellation of duty cycle detector Nov 1, 2018 Issued
Array ( [id] => 15730267 [patent_doc_number] => 10613561 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-07 [patent_title] => Device and method for calibrating a voltage regulator [patent_app_type] => utility [patent_app_number] => 16/174374 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 5418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174374 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174374
Device and method for calibrating a voltage regulator Oct 29, 2018 Issued
Array ( [id] => 15518905 [patent_doc_number] => 10566046 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-18 [patent_title] => Protocol compliant high-speed DDR transmitter [patent_app_type] => utility [patent_app_number] => 16/175577 [patent_app_country] => US [patent_app_date] => 2018-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4293 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16175577 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/175577
Protocol compliant high-speed DDR transmitter Oct 29, 2018 Issued
Array ( [id] => 16234635 [patent_doc_number] => 10742204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Semiconductor device and power module [patent_app_type] => utility [patent_app_number] => 16/174252 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8591 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16174252 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/174252
Semiconductor device and power module Oct 28, 2018 Issued
Array ( [id] => 15642599 [patent_doc_number] => 10594317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Bleeding switching regulator power rail through switching regulator ground side switch [patent_app_type] => utility [patent_app_number] => 16/173268 [patent_app_country] => US [patent_app_date] => 2018-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3173 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16173268 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/173268
Bleeding switching regulator power rail through switching regulator ground side switch Oct 28, 2018 Issued
Array ( [id] => 14860527 [patent_doc_number] => 10419007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Digital frequency-division phase-locked loop [patent_app_type] => utility [patent_app_number] => 16/169378 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5119 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169378 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169378
Digital frequency-division phase-locked loop Oct 23, 2018 Issued
Array ( [id] => 15704867 [patent_doc_number] => 10608626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Driving apparatus and semiconductor device [patent_app_type] => utility [patent_app_number] => 16/167562 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7334 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16167562 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/167562
Driving apparatus and semiconductor device Oct 22, 2018 Issued
Array ( [id] => 15402039 [patent_doc_number] => 10541685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Multiplexing latch circuit and method [patent_app_type] => utility [patent_app_number] => 16/166752 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16166752 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/166752
Multiplexing latch circuit and method Oct 21, 2018 Issued
Array ( [id] => 14632461 [patent_doc_number] => 20190229603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => GATE DRIVER [patent_app_type] => utility [patent_app_number] => 16/165257 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165257 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165257
Gate driver Oct 18, 2018 Issued
Array ( [id] => 14800645 [patent_doc_number] => 10403330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-03 [patent_title] => Power noise reduction technique for high density memory with gating [patent_app_type] => utility [patent_app_number] => 16/163720 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3092 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163720 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163720
Power noise reduction technique for high density memory with gating Oct 17, 2018 Issued
Array ( [id] => 16908602 [patent_doc_number] => 11040624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Cooling strategy for battery systems [patent_app_type] => utility [patent_app_number] => 16/160369 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 23772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/160369
Cooling strategy for battery systems Oct 14, 2018 Issued
Array ( [id] => 16908602 [patent_doc_number] => 11040624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-22 [patent_title] => Cooling strategy for battery systems [patent_app_type] => utility [patent_app_number] => 16/160369 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 23772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/160369
Cooling strategy for battery systems Oct 14, 2018 Issued
Array ( [id] => 16365196 [patent_doc_number] => 20200321947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => LOGIC CIRCUIT, SEQUENCE CIRCUIT, POWER SUPPLY CONTROL CIRCUIT, SWITCHING POWER SUPPLY DEVICE [patent_app_type] => utility [patent_app_number] => 16/753458 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5942 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16753458 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/753458
Logic circuit, sequence circuit, power supply control circuit, switching power supply device Sep 30, 2018 Issued
Array ( [id] => 16181136 [patent_doc_number] => 20200228105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => CLOCKING CIRCUIT ARRANGEMENT AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/648192 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16648192 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/648192
CLOCKING CIRCUIT ARRANGEMENT AND METHOD OF FORMING THE SAME Sep 30, 2018 Abandoned
Array ( [id] => 13629233 [patent_doc_number] => 20180366169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A CLOCK ADJUSTMENT CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/110865 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8479 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110865 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/110865
Semiconductor device including a clock adjustment circuit Aug 22, 2018 Issued
Menu