Search

Charles E. Phillips

Examiner (ID: 298)

Most Active Art Unit
3751
Art Unit(s)
3751, 3105, 2403
Total Applications
2438
Issued Applications
1788
Pending Applications
61
Abandoned Applications
589

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14039095 [patent_doc_number] => 10231317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Digital load control system providing power and communication via existing power wiring [patent_app_type] => utility [patent_app_number] => 15/589472 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 25062 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15589472 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/589472
Digital load control system providing power and communication via existing power wiring May 7, 2017 Issued
Array ( [id] => 15505007 [patent_doc_number] => 20200052692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SWITCHING ELEMENT CONTROL CIRCUIT AND POWER MODULE [patent_app_type] => utility [patent_app_number] => 16/605803 [patent_app_country] => US [patent_app_date] => 2017-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16605803 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/605803
Switching element control circuit and power module Apr 24, 2017 Issued
Array ( [id] => 11926309 [patent_doc_number] => 09793904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-17 [patent_title] => 'System and method of noise correcting PLL frequency synthesizers' [patent_app_type] => utility [patent_app_number] => 15/469434 [patent_app_country] => US [patent_app_date] => 2017-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4890 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15469434 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/469434
System and method of noise correcting PLL frequency synthesizers Mar 23, 2017 Issued
Array ( [id] => 13664433 [patent_doc_number] => 10162376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Charge pump with temporally-varying adiabaticity [patent_app_type] => utility [patent_app_number] => 15/460596 [patent_app_country] => US [patent_app_date] => 2017-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6423 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15460596 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/460596
Charge pump with temporally-varying adiabaticity Mar 15, 2017 Issued
Array ( [id] => 14025697 [patent_doc_number] => 20190074842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => FRACTIONAL-N PHASE LOCK LOOP APPARATUS AND METHOD USING MULTI-ELEMENT FRACTIONAL DIVIDERS [patent_app_type] => utility [patent_app_number] => 16/084997 [patent_app_country] => US [patent_app_date] => 2017-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16084997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/084997
Fractional-N phase lock loop apparatus and method using multi-element fractional dividers Mar 14, 2017 Issued
Array ( [id] => 11708007 [patent_doc_number] => 20170176506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'METHOD FOR USING AN ACCURATE ADJUSTABLE HIGH-FREQUENCY PHASE-DETECTOR' [patent_app_type] => utility [patent_app_number] => 15/450536 [patent_app_country] => US [patent_app_date] => 2017-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6637 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15450536 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/450536
METHOD FOR USING AN ACCURATE ADJUSTABLE HIGH-FREQUENCY PHASE-DETECTOR Mar 5, 2017 Abandoned
Array ( [id] => 14527265 [patent_doc_number] => 10340906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Integrated bootstrap high-voltage driver chip and technological structure thereof [patent_app_type] => utility [patent_app_number] => 15/779432 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9285 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15779432 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/779432
Integrated bootstrap high-voltage driver chip and technological structure thereof Jan 22, 2017 Issued
Array ( [id] => 15923619 [patent_doc_number] => 10659062 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-19 [patent_title] => PLL circuit [patent_app_type] => utility [patent_app_number] => 16/342825 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4972 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16342825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/342825
PLL circuit Dec 14, 2016 Issued
Array ( [id] => 11516058 [patent_doc_number] => 20170083132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/364459 [patent_app_country] => US [patent_app_date] => 2016-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10780 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15364459 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/364459
Semiconductor device Nov 29, 2016 Issued
Array ( [id] => 13240185 [patent_doc_number] => 10133290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-20 [patent_title] => System for balancing the voltage of series-connected semiconductor elements [patent_app_type] => utility [patent_app_number] => 15/363648 [patent_app_country] => US [patent_app_date] => 2016-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2633 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15363648 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/363648
System for balancing the voltage of series-connected semiconductor elements Nov 28, 2016 Issued
Array ( [id] => 13244411 [patent_doc_number] => 10135425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-20 [patent_title] => Power saving latches [patent_app_type] => utility [patent_app_number] => 15/361870 [patent_app_country] => US [patent_app_date] => 2016-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15361870 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/361870
Power saving latches Nov 27, 2016 Issued
Array ( [id] => 13770801 [patent_doc_number] => 10177754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Method and apparatus for generating PWM signal [patent_app_type] => utility [patent_app_number] => 15/357541 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4263 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357541 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357541
Method and apparatus for generating PWM signal Nov 20, 2016 Issued
Array ( [id] => 11495622 [patent_doc_number] => 20170069807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'COLOR FILTER AND COLOR FILTER ARRAY PANEL' [patent_app_type] => utility [patent_app_number] => 15/357000 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3526 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357000 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357000
Color filter and color filter array panel Nov 20, 2016 Issued
Array ( [id] => 13976915 [patent_doc_number] => 10217826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate [patent_app_type] => utility [patent_app_number] => 15/356601 [patent_app_country] => US [patent_app_date] => 2016-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8979 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356601 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356601
Apparatus of a metal-oxide-semiconductor (MOS) transistor including a multi-split gate Nov 19, 2016 Issued
Array ( [id] => 14065109 [patent_doc_number] => 10236869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Superconducting transmission driver system [patent_app_type] => utility [patent_app_number] => 15/356049 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356049 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356049
Superconducting transmission driver system Nov 17, 2016 Issued
Array ( [id] => 13756261 [patent_doc_number] => 10171089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications [patent_app_type] => utility [patent_app_number] => 15/354808 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5742 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15354808 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/354808
PVT-free calibration function using a doubler circuit for TDC resolution in ADPLL applications Nov 16, 2016 Issued
Array ( [id] => 13072185 [patent_doc_number] => 10056886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Continuously variable saturable shunt reactor [patent_app_type] => utility [patent_app_number] => 15/348548 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4270 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348548 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348548
Continuously variable saturable shunt reactor Nov 9, 2016 Issued
Array ( [id] => 11840160 [patent_doc_number] => 20170221880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'TUNABLE DEVICE HAVING A FET INTEGRATED WITH A BJT' [patent_app_type] => utility [patent_app_number] => 15/348878 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5366 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348878 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348878
Tunable device having a FET integrated with a BJT Nov 9, 2016 Issued
Array ( [id] => 11496037 [patent_doc_number] => 20170070222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'ADAPTIVE BLANKING TIMER FOR SHORT CIRCUIT DETECTION' [patent_app_type] => utility [patent_app_number] => 15/347380 [patent_app_country] => US [patent_app_date] => 2016-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5656 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15347380 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/347380
Masking vd to vref after miller plateau and gate charge Nov 8, 2016 Issued
Array ( [id] => 13894979 [patent_doc_number] => 10200048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Phase-locked loop (PLL) circuit [patent_app_type] => utility [patent_app_number] => 15/346248 [patent_app_country] => US [patent_app_date] => 2016-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15346248 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/346248
Phase-locked loop (PLL) circuit Nov 7, 2016 Issued
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