
Charles E. Phillips
Examiner (ID: 298)
| Most Active Art Unit | 3751 |
| Art Unit(s) | 3751, 3105, 2403 |
| Total Applications | 2438 |
| Issued Applications | 1788 |
| Pending Applications | 61 |
| Abandoned Applications | 589 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
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[patent_title] => Digital load control system providing power and communication via existing power wiring
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[patent_title] => SWITCHING ELEMENT CONTROL CIRCUIT AND POWER MODULE
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