Search

Charles E. Phillips

Examiner (ID: 69)

Most Active Art Unit
3751
Art Unit(s)
2403, 3105, 3751
Total Applications
2438
Issued Applications
1788
Pending Applications
61
Abandoned Applications
589

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19858250 [patent_doc_number] => 12261101 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Semiconductor package having wettable lead flanks and tie bars and method of making the same [patent_app_type] => utility [patent_app_number] => 17/852356 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3418 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17852356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/852356
Semiconductor package having wettable lead flanks and tie bars and method of making the same Jun 27, 2022 Issued
Array ( [id] => 18679955 [patent_doc_number] => 20230317613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/848779 [patent_app_country] => US [patent_app_date] => 2022-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4876 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848779 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848779
Semiconductor package and method of forming the same with dielectric layer disposed between protective mold structure and stepped structure of side portion of semiconductor die Jun 23, 2022 Issued
Array ( [id] => 18008574 [patent_doc_number] => 20220367341 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/842945 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842945 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842945
Semiconductor structure with shielding structure for through silicon via and manufacturing method thereof Jun 16, 2022 Issued
Array ( [id] => 19444507 [patent_doc_number] => 12094797 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-17 [patent_title] => Pressing device for directly or indirectly applying pressure to power-semiconductor components of a power-semiconductor module [patent_app_type] => utility [patent_app_number] => 17/840405 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 4987 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840405
Pressing device for directly or indirectly applying pressure to power-semiconductor components of a power-semiconductor module Jun 13, 2022 Issued
Array ( [id] => 18068212 [patent_doc_number] => 20220399300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-15 [patent_title] => CLIP STRUCTURE FOR SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/839479 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6200 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17839479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/839479
Clip structure for semiconductor package and semiconductor package including the same Jun 13, 2022 Issued
Array ( [id] => 18564731 [patent_doc_number] => 11730001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Tunnel magnetoresistive effect element, magnetic memory, and built-in memory [patent_app_type] => utility [patent_app_number] => 17/835458 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10085 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17835458 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/835458
Tunnel magnetoresistive effect element, magnetic memory, and built-in memory Jun 7, 2022 Issued
Array ( [id] => 17900864 [patent_doc_number] => 20220310526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => DIFFUSION BARRIER LAYER FOR CONDUCTIVE VIA TO DECREASE CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 17/834148 [patent_app_country] => US [patent_app_date] => 2022-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10914 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834148 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834148
Diffusion barrier layer for conductive via to decrease contact resistance Jun 6, 2022 Issued
Array ( [id] => 17871037 [patent_doc_number] => 20220293774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => METHOD FOR FORMING FIN FIELD EFFECT TRANSISTOR (FINFET) WITH A LINER LAYER [patent_app_type] => utility [patent_app_number] => 17/827327 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827327 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827327
Method for forming fin field effect transistor (FinFET) with a liner layer May 26, 2022 Issued
Array ( [id] => 18983614 [patent_doc_number] => 11908803 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor devices with flexible connector array [patent_app_type] => utility [patent_app_number] => 17/750665 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 5471 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750665 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750665
Semiconductor devices with flexible connector array May 22, 2022 Issued
Array ( [id] => 17855405 [patent_doc_number] => 20220285448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/751064 [patent_app_country] => US [patent_app_date] => 2022-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17751064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/751064
Organic light-emitting display apparatus comprising quantum dots May 22, 2022 Issued
Array ( [id] => 17840707 [patent_doc_number] => 20220278013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => Electronic package with multiple electronic components spaced apart by grooves [patent_app_type] => utility [patent_app_number] => 17/747900 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747900 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747900
Electronic package with multiple electronic components spaced apart by grooves May 17, 2022 Issued
Array ( [id] => 17840701 [patent_doc_number] => 20220278007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => ELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 17/745022 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745022
Electronic component including protective layer May 15, 2022 Issued
Array ( [id] => 18696395 [patent_doc_number] => 20230326833 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => PACKAGED COMPONENT WITH COMPOSITE PIN STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/741872 [patent_app_country] => US [patent_app_date] => 2022-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3207 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17741872 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/741872
Packaged component with composite pin structure and manufacturing method thereof May 10, 2022 Issued
Array ( [id] => 17780375 [patent_doc_number] => 20220246725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS [patent_app_type] => utility [patent_app_number] => 17/728588 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2038 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728588 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728588
SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS Apr 24, 2022 Abandoned
Array ( [id] => 17780153 [patent_doc_number] => 20220246503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-04 [patent_title] => EMBEDDED DIE PACKAGING FOR POWER SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/728220 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728220 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/728220
Embedded die packaging for power semiconductor devices Apr 24, 2022 Issued
Array ( [id] => 18983512 [patent_doc_number] => 11908699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor packages with die including cavities [patent_app_type] => utility [patent_app_number] => 17/660477 [patent_app_country] => US [patent_app_date] => 2022-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 123 [patent_no_of_words] => 37305 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17660477 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/660477
Semiconductor packages with die including cavities Apr 24, 2022 Issued
Array ( [id] => 17949406 [patent_doc_number] => 20220336425 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-20 [patent_title] => LIGHT EMITTING DIODE COMPONENT AND LIGHT EMITTING DIODE CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/723856 [patent_app_country] => US [patent_app_date] => 2022-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/723856
Light emitting diode component and light emitting diode circuit comprising p-n diodes in series Apr 18, 2022 Issued
Array ( [id] => 20177572 [patent_doc_number] => 12396338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => OLED display panel with an opening defined in an insulation layer corresonding to anode, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/755149 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 3356 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17755149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/755149
OLED display panel with an opening defined in an insulation layer corresonding to anode, and manufacturing method thereof Apr 14, 2022 Issued
Array ( [id] => 20177572 [patent_doc_number] => 12396338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => OLED display panel with an opening defined in an insulation layer corresonding to anode, and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/755149 [patent_app_country] => US [patent_app_date] => 2022-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 3356 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17755149 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/755149
OLED display panel with an opening defined in an insulation layer corresonding to anode, and manufacturing method thereof Apr 14, 2022 Issued
Array ( [id] => 19906543 [patent_doc_number] => 12283562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Clip design and method of controlling clip position [patent_app_type] => utility [patent_app_number] => 17/658881 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 5721 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17658881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/658881
Clip design and method of controlling clip position Apr 11, 2022 Issued
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