Charles H. Nolan Jr.

Array ( [id] => 20776921 [patent_doc_number] => 12660619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-16 [patent_title] => Semiconductor device structure with efficient heat-removal structures across the chip and monolithic fabrication method therefor [patent_app_type] => utility [patent_app_number] => 19/308943 [patent_app_country] => US [patent_app_date] => 2025-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 36 [patent_no_of_words] => 1227 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19308943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20028781 [patent_doc_number] => 20250167003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => EMBEDDED COMPONENT INTERPOSER OR SUBSTRATE COMPRISING DISPLACEMENT COMPENSATION TRACES (DCTs) AND METHOD OF MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 18/954308 [patent_app_country] => US [patent_app_date] => 2024-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954308 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500397 [patent_doc_number] => 20240339415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/743027 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8010 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19646675 [patent_doc_number] => 20240421195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/740558 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9783 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740558 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19484193 [patent_doc_number] => 20240332235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CHIP STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/741188 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20360205 [patent_doc_number] => 12476211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 18/672010 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5772 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672010 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19437960 [patent_doc_number] => 20240306458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => DISPLAY DEVICE HAVING A BENDING REGION [patent_app_type] => utility [patent_app_number] => 18/668505 [patent_app_country] => US [patent_app_date] => 2024-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18668505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19575542 [patent_doc_number] => 20240379834 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => RECESSED-GATE HIGH-ELECTRON-MOBILITY TRANSISTORS WITH DOPED BARRIERS AND ROUND GATE FOOT CORNERS [patent_app_type] => utility [patent_app_number] => 18/660342 [patent_app_country] => US [patent_app_date] => 2024-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660342 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19421013 [patent_doc_number] => 20240297137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 18/660190 [patent_app_country] => US [patent_app_date] => 2024-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20267049 [patent_doc_number] => 12438048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-07 [patent_title] => Redistribution lines with protection layers and method forming same [patent_app_type] => utility [patent_app_number] => 18/655989 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 1107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655989 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19409113 [patent_doc_number] => 20240292624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/648933 [patent_app_country] => US [patent_app_date] => 2024-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19879897 [patent_doc_number] => 20250112154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => Power, Signaling and Thermal Path Co-optimization [patent_app_type] => utility [patent_app_number] => 18/643907 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643907 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19384688 [patent_doc_number] => 20240274558 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => REDISTRIBUTION LAYERS AND METHODS OF FABRICATING THE SAME IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/641836 [patent_app_country] => US [patent_app_date] => 2024-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7963 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18641836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19349295 [patent_doc_number] => 20240258259 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH CONDUCTIVE BUMPS [patent_app_type] => utility [patent_app_number] => 18/635274 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8008 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19335621 [patent_doc_number] => 20240250051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => SEMICONDUCTOR CHIP HAVING STEPPED CONDUCTIVE PILLARS [patent_app_type] => utility [patent_app_number] => 18/627896 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18627896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19500478 [patent_doc_number] => 20240339496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR DIES WITH ROUNDED OR CHAMFERED EDGES [patent_app_type] => utility [patent_app_number] => 18/624811 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19470613 [patent_doc_number] => 20240324283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/613104 [patent_app_country] => US [patent_app_date] => 2024-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20175945 [patent_doc_number] => 12394701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Semiconductor package including a redistribution substrate and a method of fabricating the same [patent_app_type] => utility [patent_app_number] => 18/612193 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5724 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18612193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19821078 [patent_doc_number] => 20250079285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => POWER MODULE [patent_app_type] => utility [patent_app_number] => 18/613005 [patent_app_country] => US [patent_app_date] => 2024-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613005 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19788586 [patent_doc_number] => 20250062265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/605859 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18605859 [rel_patent_id] =>[rel_patent_doc_number] =>)