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Supervisory Patent Examiner (ID: 12898, Phone: (571)272-3721 , Office: P/2193 )

Most Active Art Unit
2193
Art Unit(s)
2124, 2193
Total Applications
586
Issued Applications
324
Pending Applications
35
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 949897 [patent_doc_number] => 06963895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-08 [patent_title] => 'Floating point pipeline method and circuit for fast inverse square root calculations' [patent_app_type] => utility [patent_app_number] => 09/562056 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2596 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963895.pdf [firstpage_image] =>[orig_patent_app_number] => 09562056 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562056
Floating point pipeline method and circuit for fast inverse square root calculations Apr 30, 2000 Issued
Array ( [id] => 1250160 [patent_doc_number] => 06675184 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Adaptive type signal estimator' [patent_app_type] => B1 [patent_app_number] => 09/559217 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3377 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/675/06675184.pdf [firstpage_image] =>[orig_patent_app_number] => 09559217 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559217
Adaptive type signal estimator Apr 25, 2000 Issued
Array ( [id] => 1365630 [patent_doc_number] => 06584485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => '4 to 2 adder' [patent_app_type] => B1 [patent_app_number] => 09/549766 [patent_app_country] => US [patent_app_date] => 2000-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2321 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584485.pdf [firstpage_image] =>[orig_patent_app_number] => 09549766 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/549766
4 to 2 adder Apr 13, 2000 Issued
Array ( [id] => 1573618 [patent_doc_number] => 06499044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Leading zero/one anticipator for floating point' [patent_app_type] => B1 [patent_app_number] => 09/546412 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9421 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499044.pdf [firstpage_image] =>[orig_patent_app_number] => 09546412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546412
Leading zero/one anticipator for floating point Apr 9, 2000 Issued
Array ( [id] => 1356215 [patent_doc_number] => 06591282 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Apparatus and method for a DC-Insensitive FIR filter for optical PRML channel' [patent_app_type] => B1 [patent_app_number] => 09/543147 [patent_app_country] => US [patent_app_date] => 2000-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 2307 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591282.pdf [firstpage_image] =>[orig_patent_app_number] => 09543147 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/543147
Apparatus and method for a DC-Insensitive FIR filter for optical PRML channel Apr 4, 2000 Issued
Array ( [id] => 1338642 [patent_doc_number] => 06601077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'DSP unit for multi-level global accumulation' [patent_app_type] => B1 [patent_app_number] => 09/541148 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601077.pdf [firstpage_image] =>[orig_patent_app_number] => 09541148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541148
DSP unit for multi-level global accumulation Mar 30, 2000 Issued
09/539922 Multipler architecture in a general purpose processor optimized for efficient multi-input addition Mar 30, 2000 Abandoned
Array ( [id] => 1384821 [patent_doc_number] => 06571264 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Floating-point arithmetic device' [patent_app_type] => B1 [patent_app_number] => 09/541679 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5061 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571264.pdf [firstpage_image] =>[orig_patent_app_number] => 09541679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541679
Floating-point arithmetic device Mar 30, 2000 Issued
Array ( [id] => 1296718 [patent_doc_number] => 06633896 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method and system for multiplying large numbers' [patent_app_type] => B1 [patent_app_number] => 09/538174 [patent_app_country] => US [patent_app_date] => 2000-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3917 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633896.pdf [firstpage_image] =>[orig_patent_app_number] => 09538174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/538174
Method and system for multiplying large numbers Mar 29, 2000 Issued
Array ( [id] => 1310702 [patent_doc_number] => 06625628 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method and apparatus for digital filter' [patent_app_type] => B1 [patent_app_number] => 09/534994 [patent_app_country] => US [patent_app_date] => 2000-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3835 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625628.pdf [firstpage_image] =>[orig_patent_app_number] => 09534994 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534994
Method and apparatus for digital filter Mar 26, 2000 Issued
Array ( [id] => 1260272 [patent_doc_number] => 06668265 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Apparatus and method for outputting sequence of vectors, data recording medium, and carrier wave signal' [patent_app_type] => B1 [patent_app_number] => 09/531699 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6435 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668265.pdf [firstpage_image] =>[orig_patent_app_number] => 09531699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531699
Apparatus and method for outputting sequence of vectors, data recording medium, and carrier wave signal Mar 19, 2000 Issued
Array ( [id] => 1352396 [patent_doc_number] => 06594679 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Leading-zero anticipator having an independent sign bit determination module' [patent_app_type] => B1 [patent_app_number] => 09/531850 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4239 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594679.pdf [firstpage_image] =>[orig_patent_app_number] => 09531850 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531850
Leading-zero anticipator having an independent sign bit determination module Mar 19, 2000 Issued
Array ( [id] => 1408388 [patent_doc_number] => 06557021 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Rounding anticipator for floating point operations' [patent_app_type] => B1 [patent_app_number] => 09/527653 [patent_app_country] => US [patent_app_date] => 2000-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 48 [patent_no_of_words] => 12458 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557021.pdf [firstpage_image] =>[orig_patent_app_number] => 09527653 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527653
Rounding anticipator for floating point operations Mar 16, 2000 Issued
Array ( [id] => 1260282 [patent_doc_number] => 06668267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Device and method for the implementation of an elementary modular operation according to the Montgomery method' [patent_app_type] => B1 [patent_app_number] => 09/526782 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8359 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668267.pdf [firstpage_image] =>[orig_patent_app_number] => 09526782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526782
Device and method for the implementation of an elementary modular operation according to the Montgomery method Mar 15, 2000 Issued
Array ( [id] => 1185533 [patent_doc_number] => 06745218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-01 [patent_title] => 'Adaptive digital filter' [patent_app_type] => B1 [patent_app_number] => 09/527404 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11311 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/745/06745218.pdf [firstpage_image] =>[orig_patent_app_number] => 09527404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527404
Adaptive digital filter Mar 15, 2000 Issued
Array ( [id] => 7633178 [patent_doc_number] => 06658442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Device and method for the implementation of an elementary modular operation according to the Montgomery method' [patent_app_type] => B1 [patent_app_number] => 09/526228 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 7939 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658442.pdf [firstpage_image] =>[orig_patent_app_number] => 09526228 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/526228
Device and method for the implementation of an elementary modular operation according to the Montgomery method Mar 14, 2000 Issued
Array ( [id] => 1423019 [patent_doc_number] => 06539413 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Prefix tree adder with efficient sum generation' [patent_app_type] => B1 [patent_app_number] => 09/525644 [patent_app_country] => US [patent_app_date] => 2000-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4239 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539413.pdf [firstpage_image] =>[orig_patent_app_number] => 09525644 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/525644
Prefix tree adder with efficient sum generation Mar 14, 2000 Issued
Array ( [id] => 1394101 [patent_doc_number] => 06567832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Device, method, and storage medium for exponentiation and elliptic curve exponentiation' [patent_app_type] => B1 [patent_app_number] => 09/523486 [patent_app_country] => US [patent_app_date] => 2000-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 7973 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567832.pdf [firstpage_image] =>[orig_patent_app_number] => 09523486 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/523486
Device, method, and storage medium for exponentiation and elliptic curve exponentiation Mar 9, 2000 Issued
Array ( [id] => 1288608 [patent_doc_number] => 06647405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-11 [patent_title] => 'Adder circuit, integrating circuit which uses the adder circuit, and synchronism detection circuit which uses the integrating circuit' [patent_app_type] => B1 [patent_app_number] => 09/522404 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4975 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647405.pdf [firstpage_image] =>[orig_patent_app_number] => 09522404 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522404
Adder circuit, integrating circuit which uses the adder circuit, and synchronism detection circuit which uses the integrating circuit Mar 8, 2000 Issued
Array ( [id] => 1384897 [patent_doc_number] => 06571267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Floating point addition/subtraction execution unit' [patent_app_type] => B1 [patent_app_number] => 09/521891 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 16300 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 488 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571267.pdf [firstpage_image] =>[orig_patent_app_number] => 09521891 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/521891
Floating point addition/subtraction execution unit Mar 8, 2000 Issued
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