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Supervisory Patent Examiner (ID: 12898, Phone: (571)272-3721 , Office: P/2193 )

Most Active Art Unit
2193
Art Unit(s)
2124, 2193
Total Applications
586
Issued Applications
324
Pending Applications
35
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
09/521597 Graphics processing unit and graphics processing system Mar 8, 2000 Abandoned
Array ( [id] => 517452 [patent_doc_number] => 07203714 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-04-10 [patent_title] => 'Logic circuit' [patent_app_type] => utility [patent_app_number] => 09/522470 [patent_app_country] => US [patent_app_date] => 2000-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 31 [patent_no_of_words] => 33413 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/203/07203714.pdf [firstpage_image] =>[orig_patent_app_number] => 09522470 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/522470
Logic circuit Mar 8, 2000 Issued
Array ( [id] => 1297746 [patent_doc_number] => 06631390 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-07 [patent_title] => 'Method and apparatus for generating random numbers using flip-flop meta-stability' [patent_app_type] => B1 [patent_app_number] => 09/519549 [patent_app_country] => US [patent_app_date] => 2000-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3724 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631390.pdf [firstpage_image] =>[orig_patent_app_number] => 09519549 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/519549
Method and apparatus for generating random numbers using flip-flop meta-stability Mar 5, 2000 Issued
Array ( [id] => 1338672 [patent_doc_number] => 06601080 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Hybrid representation scheme for factor L in sparse direct matrix factorization' [patent_app_type] => B1 [patent_app_number] => 09/510911 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7276 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601080.pdf [firstpage_image] =>[orig_patent_app_number] => 09510911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510911
Hybrid representation scheme for factor L in sparse direct matrix factorization Feb 22, 2000 Issued
Array ( [id] => 962043 [patent_doc_number] => 06952709 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-04 [patent_title] => 'Receiver, programmable circuit and method of calculating digital filters' [patent_app_type] => utility [patent_app_number] => 09/510852 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/952/06952709.pdf [firstpage_image] =>[orig_patent_app_number] => 09510852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510852
Receiver, programmable circuit and method of calculating digital filters Feb 22, 2000 Issued
Array ( [id] => 1296712 [patent_doc_number] => 06633895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Apparatus and method for sharing overflow/underflow compare hardware in a floating-point multiply-accumulate (FMAC) or floating-point adder (FADD) unit' [patent_app_type] => B1 [patent_app_number] => 09/507861 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 24 [patent_no_of_words] => 7072 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/633/06633895.pdf [firstpage_image] =>[orig_patent_app_number] => 09507861 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507861
Apparatus and method for sharing overflow/underflow compare hardware in a floating-point multiply-accumulate (FMAC) or floating-point adder (FADD) unit Feb 21, 2000 Issued
Array ( [id] => 1364460 [patent_doc_number] => 06581082 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Reduced gate count differentiator' [patent_app_type] => B1 [patent_app_number] => 09/510763 [patent_app_country] => US [patent_app_date] => 2000-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4069 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581082.pdf [firstpage_image] =>[orig_patent_app_number] => 09510763 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510763
Reduced gate count differentiator Feb 21, 2000 Issued
Array ( [id] => 1221502 [patent_doc_number] => 06708193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Linear summation multiplier array implementation for both signed and unsigned multiplication' [patent_app_type] => B1 [patent_app_number] => 09/510274 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 20 [patent_no_of_words] => 11270 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708193.pdf [firstpage_image] =>[orig_patent_app_number] => 09510274 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510274
Linear summation multiplier array implementation for both signed and unsigned multiplication Feb 20, 2000 Issued
Array ( [id] => 1384851 [patent_doc_number] => 06571266 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Method for acquiring FMAC rounding parameters' [patent_app_type] => B1 [patent_app_number] => 09/510284 [patent_app_country] => US [patent_app_date] => 2000-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5348 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571266.pdf [firstpage_image] =>[orig_patent_app_number] => 09510284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/510284
Method for acquiring FMAC rounding parameters Feb 20, 2000 Issued
Array ( [id] => 748952 [patent_doc_number] => 07031993 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method and apparatus for fast natural log(X) calculation' [patent_app_type] => utility [patent_app_number] => 09/507521 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2608 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031993.pdf [firstpage_image] =>[orig_patent_app_number] => 09507521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507521
Method and apparatus for fast natural log(X) calculation Feb 17, 2000 Issued
Array ( [id] => 1176938 [patent_doc_number] => 06760742 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-06 [patent_title] => 'Multi-dimensional galois field multiplier' [patent_app_type] => B1 [patent_app_number] => 09/507187 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4999 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/760/06760742.pdf [firstpage_image] =>[orig_patent_app_number] => 09507187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/507187
Multi-dimensional galois field multiplier Feb 17, 2000 Issued
Array ( [id] => 1017086 [patent_doc_number] => 06895420 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'Apparatus and method for sharing data FET for a four-way multiplexer' [patent_app_type] => utility [patent_app_number] => 09/505382 [patent_app_country] => US [patent_app_date] => 2000-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3097 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/895/06895420.pdf [firstpage_image] =>[orig_patent_app_number] => 09505382 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/505382
Apparatus and method for sharing data FET for a four-way multiplexer Feb 15, 2000 Issued
Array ( [id] => 1242956 [patent_doc_number] => 06684236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'System of and method for efficiently performing computations through extended booth encoding of the operands thereto' [patent_app_type] => B1 [patent_app_number] => 09/504392 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3040 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684236.pdf [firstpage_image] =>[orig_patent_app_number] => 09504392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504392
System of and method for efficiently performing computations through extended booth encoding of the operands thereto Feb 14, 2000 Issued
Array ( [id] => 1186208 [patent_doc_number] => 06742011 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry' [patent_app_type] => B1 [patent_app_number] => 09/504984 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6191 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742011.pdf [firstpage_image] =>[orig_patent_app_number] => 09504984 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/504984
Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry Feb 14, 2000 Issued
Array ( [id] => 477890 [patent_doc_number] => 07231414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-12 [patent_title] => 'Apparatus and method for performing addition of PKG recoded numbers' [patent_app_type] => utility [patent_app_number] => 09/501045 [patent_app_country] => US [patent_app_date] => 2000-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 3199 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/231/07231414.pdf [firstpage_image] =>[orig_patent_app_number] => 09501045 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501045
Apparatus and method for performing addition of PKG recoded numbers Feb 8, 2000 Issued
Array ( [id] => 1169197 [patent_doc_number] => 06766343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method and apparatus for coordinate system conversions' [patent_app_type] => B1 [patent_app_number] => 09/499061 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6926 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766343.pdf [firstpage_image] =>[orig_patent_app_number] => 09499061 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/499061
Method and apparatus for coordinate system conversions Feb 3, 2000 Issued
Array ( [id] => 1129300 [patent_doc_number] => 06795838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Apparatus and method for transforming mathematical expression, and storage medium' [patent_app_type] => B1 [patent_app_number] => 09/498011 [patent_app_country] => US [patent_app_date] => 2000-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 9018 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795838.pdf [firstpage_image] =>[orig_patent_app_number] => 09498011 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/498011
Apparatus and method for transforming mathematical expression, and storage medium Feb 3, 2000 Issued
Array ( [id] => 1184335 [patent_doc_number] => 06748407 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Direct digital synthesizer' [patent_app_type] => B1 [patent_app_number] => 09/495912 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3712 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748407.pdf [firstpage_image] =>[orig_patent_app_number] => 09495912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/495912
Direct digital synthesizer Feb 1, 2000 Issued
Array ( [id] => 1399987 [patent_doc_number] => 06564238 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Data processing apparatus and method for performing different word-length arithmetic operations' [patent_app_type] => B1 [patent_app_number] => 09/497063 [patent_app_country] => US [patent_app_date] => 2000-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8777 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564238.pdf [firstpage_image] =>[orig_patent_app_number] => 09497063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/497063
Data processing apparatus and method for performing different word-length arithmetic operations Feb 1, 2000 Issued
Array ( [id] => 1410397 [patent_doc_number] => 06553394 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Continuous memoization' [patent_app_type] => B1 [patent_app_number] => 09/488584 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2300 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553394.pdf [firstpage_image] =>[orig_patent_app_number] => 09488584 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488584
Continuous memoization Jan 20, 2000 Issued
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