Chat C. Do

Array ( [id] => 4685632 [patent_doc_number] => 20080029813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/882854 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3942 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029813.pdf [firstpage_image] =>[orig_patent_app_number] => 11882854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4685190 [patent_doc_number] => 20080029371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-07 [patent_title] => 'TRANSISTOR AND ITS METHOD OF MANUFACTURE' [patent_app_type] => utility [patent_app_number] => 11/832592 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20080029371.pdf [firstpage_image] =>[orig_patent_app_number] => 11832592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5256697 [patent_doc_number] => 20070210329 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-13 [patent_title] => 'WARP-FREE SEMICONDUCTOR WAFER, AND DEVICES USING THE SAME' [patent_app_type] => utility [patent_app_number] => 11/683222 [patent_app_country] => US [patent_app_date] => 2007-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6156 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20070210329.pdf [firstpage_image] =>[orig_patent_app_number] => 11683222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4749196 [patent_doc_number] => 20080157267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'Stacked Printed Devices on a Carrier Substrate' [patent_app_type] => utility [patent_app_number] => 11/680503 [patent_app_country] => US [patent_app_date] => 2007-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3243 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157267.pdf [firstpage_image] =>[orig_patent_app_number] => 11680503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4809488 [patent_doc_number] => 20080190119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'PACKAGE FOR HOUSING A SEMICONDUCTOR CHIP AND METHOD FOR OPERATING A SEMICONDUCTOR CHIP AT LESS-THAN-AMBIENT TEMPERATURES' [patent_app_type] => utility [patent_app_number] => 11/672942 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20080190119.pdf [firstpage_image] =>[orig_patent_app_number] => 11672942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4811157 [patent_doc_number] => 20080191788 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-14 [patent_title] => 'SOI MOSFET DEVICE WITH ADJUSTABLE THRESHOLD VOLTAGE' [patent_app_type] => utility [patent_app_number] => 11/672592 [patent_app_country] => US [patent_app_date] => 2007-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 4850 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0191/20080191788.pdf [firstpage_image] =>[orig_patent_app_number] => 11672592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4564551 [patent_doc_number] => 07838991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Metallurgy for copper plated wafers' [patent_app_type] => utility [patent_app_number] => 11/671422 [patent_app_country] => US [patent_app_date] => 2007-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3762 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/838/07838991.pdf [firstpage_image] =>[orig_patent_app_number] => 11671422 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 45166 [patent_doc_number] => 07777310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Integrated circuit package system with integral inner lead and paddle' [patent_app_type] => utility [patent_app_number] => 11/670862 [patent_app_country] => US [patent_app_date] => 2007-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5338 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777310.pdf [firstpage_image] =>[orig_patent_app_number] => 11670862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5236619 [patent_doc_number] => 20070128776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-07 [patent_title] => 'ISOLATED FULLY DEPLETED SILICON-ON-INSULATOR REGIONS BY SELECTIVE ETCH' [patent_app_type] => utility [patent_app_number] => 11/670262 [patent_app_country] => US [patent_app_date] => 2007-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3052 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20070128776.pdf [firstpage_image] =>[orig_patent_app_number] => 11670262 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4843183 [patent_doc_number] => 20080179591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Phase Change Memory Cell Design with Adjusted Seam Location' [patent_app_type] => utility [patent_app_number] => 11/668992 [patent_app_country] => US [patent_app_date] => 2007-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20080179591.pdf [firstpage_image] =>[orig_patent_app_number] => 11668992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5157424 [patent_doc_number] => 20070170468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'Method for manufacturing a semiconductor substrate and a method for manufacturing a semiconductor device and the semiconductor device manufactured thereby' [patent_app_type] => utility [patent_app_number] => 11/653502 [patent_app_country] => US [patent_app_date] => 2007-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5768 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20070170468.pdf [firstpage_image] =>[orig_patent_app_number] => 11653502 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4971519 [patent_doc_number] => 20070111521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-17 [patent_title] => 'Surface preparation prior to deposition on germanium' [patent_app_type] => utility [patent_app_number] => 11/651324 [patent_app_country] => US [patent_app_date] => 2007-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8135 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20070111521.pdf [firstpage_image] =>[orig_patent_app_number] => 11651324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5245140 [patent_doc_number] => 20070241374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Solid-state image sensing apparatus and fabrication method therefor' [patent_app_type] => utility [patent_app_number] => 11/651022 [patent_app_country] => US [patent_app_date] => 2007-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4362 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20070241374.pdf [firstpage_image] =>[orig_patent_app_number] => 11651022 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5098388 [patent_doc_number] => 20070181648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Electronic device and process for forming same' [patent_app_type] => utility [patent_app_number] => 11/644440 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10604 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20070181648.pdf [firstpage_image] =>[orig_patent_app_number] => 11644440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5160013 [patent_doc_number] => 20070173057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-26 [patent_title] => 'METHOD FOR FABRICATING STORAGE NODE CONTACT IN SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 11/567213 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3496 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20070173057.pdf [firstpage_image] =>[orig_patent_app_number] => 11567213 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4833500 [patent_doc_number] => 20080132047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'METHOD FOR DOPING IMPURITIES' [patent_app_type] => utility [patent_app_number] => 11/566814 [patent_app_country] => US [patent_app_date] => 2006-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3851 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20080132047.pdf [firstpage_image] =>[orig_patent_app_number] => 11566814 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4829316 [patent_doc_number] => 20080128821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology' [patent_app_type] => utility [patent_app_number] => 11/566263 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20080128821.pdf [firstpage_image] =>[orig_patent_app_number] => 11566263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4526638 [patent_doc_number] => 07952123 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Thin film transistor substrate and display device' [patent_app_type] => utility [patent_app_number] => 12/090883 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 7828 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952123.pdf [firstpage_image] =>[orig_patent_app_number] => 12090883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5247414 [patent_doc_number] => 20070243648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'MANUFACTURING METHOD OF PIXEL STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/563824 [patent_app_country] => US [patent_app_date] => 2006-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5391 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20070243648.pdf [firstpage_image] =>[orig_patent_app_number] => 11563824 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 82824 [patent_doc_number] => 07745893 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Magnetic transistor structure' [patent_app_type] => utility [patent_app_number] => 11/539284 [patent_app_country] => US [patent_app_date] => 2006-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2500 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/745/07745893.pdf [firstpage_image] =>[orig_patent_app_number] => 11539284 [rel_patent_id] =>[rel_patent_doc_number] =>)