Search

Chee-chong Lee

Examiner (ID: 9728, Phone: (571)270-1916 , Office: P/3752 )

Most Active Art Unit
3752
Art Unit(s)
3752
Total Applications
921
Issued Applications
490
Pending Applications
140
Abandoned Applications
313

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20145704 [patent_doc_number] => 12380047 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Expanded data link width for main band chip module connection in alternate modes [patent_app_type] => utility [patent_app_number] => 18/352600 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7379 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18352600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/352600
Expanded data link width for main band chip module connection in alternate modes Jul 13, 2023 Issued
Array ( [id] => 18960077 [patent_doc_number] => 20240048404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => ELECTRONIC DEVICE, CORRESPONDING BUS COMMUNICATION SYSTEM AND METHOD OF CONFIGURING A BUS COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/350345 [patent_app_country] => US [patent_app_date] => 2023-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10865 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18350345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/350345
Electronic device, corresponding bus communication system and method of configuring a bus communication system Jul 10, 2023 Issued
Array ( [id] => 19949831 [patent_doc_number] => 12321193 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Hierarchically-aware buffering for clock structures [patent_app_type] => utility [patent_app_number] => 18/347315 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 1091 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18347315 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/347315
Hierarchically-aware buffering for clock structures Jul 4, 2023 Issued
Array ( [id] => 19686428 [patent_doc_number] => 20250004973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => NETWORK CONNECTIVITY FOR OUT-OF-BAND PROCESSORS IN HETEROGENEOUS COMPUTING PLATFORMS [patent_app_type] => utility [patent_app_number] => 18/344940 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18413 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344940 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344940
Network connectivity for out-of-band processors in heterogeneous computing platforms Jun 29, 2023 Issued
Array ( [id] => 19949938 [patent_doc_number] => 12321300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Apparatus and methods for translating transactions between one or more requesting units and a target unit [patent_app_type] => utility [patent_app_number] => 18/345992 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345992 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345992
Apparatus and methods for translating transactions between one or more requesting units and a target unit Jun 29, 2023 Issued
Array ( [id] => 19685990 [patent_doc_number] => 20250004535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => OPTIMIZED POWER MANAGEMENT FOR COMPUTER SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/344102 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344102 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344102
Optimized power management for computer systems Jun 28, 2023 Issued
Array ( [id] => 20145398 [patent_doc_number] => 12379740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-05 [patent_title] => Technique to mitigate clock generation failure at high input clock slew [patent_app_type] => utility [patent_app_number] => 18/344087 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344087 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344087
Technique to mitigate clock generation failure at high input clock slew Jun 28, 2023 Issued
Array ( [id] => 18925099 [patent_doc_number] => 20240028103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => Mechanism for Saving Power on a Bus Interface [patent_app_type] => utility [patent_app_number] => 18/337189 [patent_app_country] => US [patent_app_date] => 2023-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18337189 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/337189
Mechanism for Saving Power on a Bus Interface Jun 18, 2023 Issued
Array ( [id] => 18662490 [patent_doc_number] => 20230308512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => INDEPENDENT COMMUNICATION PATHWAYS [patent_app_type] => utility [patent_app_number] => 18/323831 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12694 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323831 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323831
Independent communication pathways May 24, 2023 Issued
Array ( [id] => 18686994 [patent_doc_number] => 11782730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-10-10 [patent_title] => Operation-specific file system [patent_app_type] => utility [patent_app_number] => 18/320648 [patent_app_country] => US [patent_app_date] => 2023-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 18004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18320648 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/320648
Operation-specific file system May 18, 2023 Issued
Array ( [id] => 18772536 [patent_doc_number] => 20230367362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-16 [patent_title] => TIMESTAMP ALIGNMENT ACROSS MULTIPLE COMPUTING NODES [patent_app_type] => utility [patent_app_number] => 18/198150 [patent_app_country] => US [patent_app_date] => 2023-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18198150 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/198150
Timestamp alignment across multiple computing nodes May 15, 2023 Issued
Array ( [id] => 20331503 [patent_doc_number] => 12461779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-04 [patent_title] => Method and apparatus for controlling running of operating system, and embedded system and chip [patent_app_type] => utility [patent_app_number] => 18/549718 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 52297 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18549718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/549718
Method and apparatus for controlling running of operating system, and embedded system and chip Apr 27, 2023 Issued
Array ( [id] => 19053234 [patent_doc_number] => 20240095203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => LOW VOLTAGE DRIVE CIRCUIT FOR SYNCHRONIZING TRANSMIT DATA FROM A HOST DEVICE TO CHANNELS ON A BUS [patent_app_type] => utility [patent_app_number] => 18/307710 [patent_app_country] => US [patent_app_date] => 2023-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20735 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18307710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/307710
Low voltage drive circuit for synchronizing transmit data from a host device to channels on a bus Apr 25, 2023 Issued
Array ( [id] => 19544782 [patent_doc_number] => 20240361818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Server Information Handling System with Power Interface Component [patent_app_type] => utility [patent_app_number] => 18/138760 [patent_app_country] => US [patent_app_date] => 2023-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18138760 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/138760
Server information handling system with power interface component Apr 24, 2023 Issued
Array ( [id] => 18586502 [patent_doc_number] => 20230268767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => METHOD AND SYSTEM FOR POWER SUPPLY CONTROL [patent_app_type] => utility [patent_app_number] => 18/137330 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7980 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18137330 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/137330
Method and system for power supply control Apr 19, 2023 Issued
Array ( [id] => 19885530 [patent_doc_number] => 12271243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Power consumption management method and apparatus [patent_app_type] => utility [patent_app_number] => 18/304100 [patent_app_country] => US [patent_app_date] => 2023-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 11684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18304100 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/304100
Power consumption management method and apparatus Apr 19, 2023 Issued
Array ( [id] => 19499033 [patent_doc_number] => 20240338051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING A CAPACITOR AND CONSTANT CURRENT SINK [patent_app_type] => utility [patent_app_number] => 18/295560 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9421 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -36 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295560 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295560
Low power and area clock monitoring circuit using a capacitor and constant current sink Apr 3, 2023 Issued
Array ( [id] => 19499207 [patent_doc_number] => 20240338225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => METHOD FOR CRITERIA-BASED DESIRED STATE MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/295759 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295759 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295759
Method for criteria-based desired state management Apr 3, 2023 Issued
Array ( [id] => 20360776 [patent_doc_number] => 12476785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-18 [patent_title] => Low power and area clock monitoring circuit using ring delay arrangement for clock signal having phase-to-phase variation [patent_app_type] => utility [patent_app_number] => 18/295537 [patent_app_country] => US [patent_app_date] => 2023-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 5869 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18295537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/295537
Low power and area clock monitoring circuit using ring delay arrangement for clock signal having phase-to-phase variation Apr 3, 2023 Issued
Array ( [id] => 19842027 [patent_doc_number] => 12254418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Systems and methods for heuristic algorithms with variable effort parameters [patent_app_type] => utility [patent_app_number] => 18/126566 [patent_app_country] => US [patent_app_date] => 2023-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8437 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18126566 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/126566
Systems and methods for heuristic algorithms with variable effort parameters Mar 26, 2023 Issued
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