
Cheung Lee
Examiner (ID: 2843)
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812, 2896, 2826 |
| Total Applications | 1894 |
| Issued Applications | 1732 |
| Pending Applications | 70 |
| Abandoned Applications | 129 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19560114
[patent_doc_number] => 20240371906
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-11-07
[patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH IMAGE SENSORS AND WAFER BONDING
[patent_app_type] => utility
[patent_app_number] => 18/778976
[patent_app_country] => US
[patent_app_date] => 2024-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18592
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18778976
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/778976 | Multilevel semiconductor device and structure with image sensors and wafer bonding | Jul 19, 2024 | Issued |
Array
(
[id] => 19484047
[patent_doc_number] => 20240332089
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => METHOD OF FORMING A GATE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 18/741998
[patent_app_country] => US
[patent_app_date] => 2024-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7446
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741998
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/741998 | Method of forming a gate structure including semiconductor material implantation into dummy gate stack | Jun 12, 2024 | Issued |
Array
(
[id] => 19483968
[patent_doc_number] => 20240332010
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-03
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 18/738742
[patent_app_country] => US
[patent_app_date] => 2024-06-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13836
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18738742
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/738742 | Semiconductor devices devices including crystallized layer having multiple crystalline orientations and methods of manufacture | Jun 9, 2024 | Issued |
Array
(
[id] => 20134034
[patent_doc_number] => 12376365
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-29
[patent_title] => Nanosheet devices with hybrid structures and methods of fabricating the same
[patent_app_type] => utility
[patent_app_number] => 18/737166
[patent_app_country] => US
[patent_app_date] => 2024-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 58
[patent_figures_cnt] => 156
[patent_no_of_words] => 8310
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18737166
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/737166 | Nanosheet devices with hybrid structures and methods of fabricating the same | Jun 6, 2024 | Issued |
Array
(
[id] => 19436278
[patent_doc_number] => 20240304776
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/665858
[patent_app_country] => US
[patent_app_date] => 2024-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4831
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 352
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18665858
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/665858 | Light-emitting device having light-emitting units including epitaxial structure and conductive structure | May 15, 2024 | Issued |
Array
(
[id] => 19421113
[patent_doc_number] => 20240297237
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-05
[patent_title] => NANOSHEET FIELD-EFFECT TRANSISTOR DEVICE AND METHOD OF FORMING
[patent_app_type] => utility
[patent_app_number] => 18/660461
[patent_app_country] => US
[patent_app_date] => 2024-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18660461
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/660461 | Nanosheet field-effect transistor device including multi-layer spacer film and method of forming | May 9, 2024 | Issued |
Array
(
[id] => 20113278
[patent_doc_number] => 12364034
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-15
[patent_title] => Imaging device and camera system including photoelectric conversion layer between two electrodes, and driving method of imaging device
[patent_app_type] => utility
[patent_app_number] => 18/659863
[patent_app_country] => US
[patent_app_date] => 2024-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 48
[patent_no_of_words] => 24093
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659863
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/659863 | Imaging device and camera system including photoelectric conversion layer between two electrodes, and driving method of imaging device | May 8, 2024 | Issued |
Array
(
[id] => 20175891
[patent_doc_number] => 12394646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-08-19
[patent_title] => In-chamber low-profile sensor assembly
[patent_app_type] => utility
[patent_app_number] => 18/659343
[patent_app_country] => US
[patent_app_date] => 2024-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 4613
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18659343
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/659343 | In-chamber low-profile sensor assembly | May 8, 2024 | Issued |
Array
(
[id] => 19392769
[patent_doc_number] => 20240282639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/650218
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10510
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650218
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/650218 | Semiconductor device including wall fin with dielectric layers disposed between gate-all-around transistors | Apr 29, 2024 | Issued |
Array
(
[id] => 19392769
[patent_doc_number] => 20240282639
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/650218
[patent_app_country] => US
[patent_app_date] => 2024-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10510
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18650218
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/650218 | Semiconductor device including wall fin with dielectric layers disposed between gate-all-around transistors | Apr 29, 2024 | Issued |
Array
(
[id] => 19420957
[patent_doc_number] => 20240297081
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-05
[patent_title] => METHOD FOR FORMING SIDEWALL SPACERS AND SEMICONDUCTOR DEVICES FABRICATED THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/646878
[patent_app_country] => US
[patent_app_date] => 2024-04-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8542
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646878
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/646878 | METHOD FOR FORMING SIDEWALL SPACERS AND SEMICONDUCTOR DEVICES FABRICATED THEREOF | Apr 25, 2024 | Pending |
Array
(
[id] => 20119645
[patent_doc_number] => 12369384
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-22
[patent_title] => Semiconductor device structure including dielectric region with plurality of different oxidation regions
[patent_app_type] => utility
[patent_app_number] => 18/643035
[patent_app_country] => US
[patent_app_date] => 2024-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 52
[patent_no_of_words] => 8189
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643035
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/643035 | Semiconductor device structure including dielectric region with plurality of different oxidation regions | Apr 22, 2024 | Issued |
Array
(
[id] => 19366094
[patent_doc_number] => 20240268128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => 3D Stackable Memory and Methods of Manufacture
[patent_app_type] => utility
[patent_app_number] => 18/637552
[patent_app_country] => US
[patent_app_date] => 2024-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637552
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/637552 | 3D Stackable Memory and Methods of Manufacture | Apr 16, 2024 | Pending |
Array
(
[id] => 19366094
[patent_doc_number] => 20240268128
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => 3D Stackable Memory and Methods of Manufacture
[patent_app_type] => utility
[patent_app_number] => 18/637552
[patent_app_country] => US
[patent_app_date] => 2024-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637552
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/637552 | 3D Stackable Memory and Methods of Manufacture | Apr 16, 2024 | Pending |
Array
(
[id] => 19945452
[patent_doc_number] => 12317602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-27
[patent_title] => Forming ESD devices using multi-gate compatible processes
[patent_app_type] => utility
[patent_app_number] => 18/623294
[patent_app_country] => US
[patent_app_date] => 2024-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 44
[patent_no_of_words] => 6948
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623294
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/623294 | Forming ESD devices using multi-gate compatible processes | Mar 31, 2024 | Issued |
Array
(
[id] => 19321642
[patent_doc_number] => 20240243189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => ISOLATION STRUCTURES FOR TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 18/622018
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622018
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/622018 | ISOLATION STRUCTURES FOR TRANSISTORS | Mar 28, 2024 | Pending |
Array
(
[id] => 19321642
[patent_doc_number] => 20240243189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-07-18
[patent_title] => ISOLATION STRUCTURES FOR TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 18/622018
[patent_app_country] => US
[patent_app_date] => 2024-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18622018
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/622018 | ISOLATION STRUCTURES FOR TRANSISTORS | Mar 28, 2024 | Pending |
Array
(
[id] => 19364188
[patent_doc_number] => 20240266222
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/613772
[patent_app_country] => US
[patent_app_date] => 2024-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 40363
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18613772
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/613772 | Manufacturing method of semiconductor device including mulitple oxides | Mar 21, 2024 | Issued |
Array
(
[id] => 19269638
[patent_doc_number] => 20240213342
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/599522
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7478
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599522
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/599522 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME | Mar 7, 2024 | Pending |
Array
(
[id] => 19269394
[patent_doc_number] => 20240213098
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => Gate Oxide Structures In Semiconductor Devices
[patent_app_type] => utility
[patent_app_number] => 18/600216
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18600216
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/600216 | Plural gate oxide structures with different thicknesses in semiconductor devices | Mar 7, 2024 | Issued |