Search

Cheung Lee

Examiner (ID: 15512, Phone: (571)272-5977 , Office: P/2896 )

Most Active Art Unit
2812
Art Unit(s)
2812, 2896, 2826
Total Applications
1957
Issued Applications
1774
Pending Applications
79
Abandoned Applications
130

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19688183 [patent_doc_number] => 20250006728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-02 [patent_title] => SELF-CLAMPING RESISTOR AND CIRCUIT FOR TRANSISTOR LINEAR REGION CURRENT MATCHING [patent_app_type] => utility [patent_app_number] => 18/345470 [patent_app_country] => US [patent_app_date] => 2023-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18345470 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/345470
SELF-CLAMPING RESISTOR AND CIRCUIT FOR TRANSISTOR LINEAR REGION CURRENT MATCHING Jun 29, 2023 Pending
Array ( [id] => 20748283 [patent_doc_number] => 12648223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Display panel and display device having different doped channel regions [patent_app_type] => utility [patent_app_number] => 18/288968 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18288968 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/288968
Display panel and display device having different doped channel regions Jun 28, 2023 Issued
Array ( [id] => 20471020 [patent_doc_number] => 12527066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Gate isolation structures and methods of forming the same [patent_app_type] => utility [patent_app_number] => 18/344400 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 3277 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18344400 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/344400
Gate isolation structures and methods of forming the same Jun 28, 2023 Issued
Array ( [id] => 19185270 [patent_doc_number] => 11991888 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => 3D stackable memory and methods of manufacture [patent_app_type] => utility [patent_app_number] => 18/343912 [patent_app_country] => US [patent_app_date] => 2023-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343912
3D stackable memory and methods of manufacture Jun 28, 2023 Issued
Array ( [id] => 19116374 [patent_doc_number] => 20240128124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => METHODS FOR FORMING STACKED TRANSISTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/343467 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18343467 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/343467
Methods for forming stacked transistor devices including a nanosheet field-effect transistor and a fin field-effect transistor Jun 27, 2023 Issued
Array ( [id] => 20471019 [patent_doc_number] => 12527065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Semiconductor device and method for forming the same [patent_app_type] => utility [patent_app_number] => 18/342918 [patent_app_country] => US [patent_app_date] => 2023-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 3288 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18342918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/342918
Semiconductor device and method for forming the same Jun 27, 2023 Issued
Array ( [id] => 18696550 [patent_doc_number] => 20230326990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => Multi-Channel Devices and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 18/334918 [patent_app_country] => US [patent_app_date] => 2023-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18334918 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/334918
Multi-channel devices and methods of manufacture Jun 13, 2023 Issued
Array ( [id] => 18696567 [patent_doc_number] => 20230327007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-12 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/333982 [patent_app_country] => US [patent_app_date] => 2023-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18333982 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/333982
Semiconductor device having source/drain contacts connecting 2-D material layer and method for forming the same Jun 12, 2023 Issued
Array ( [id] => 18679866 [patent_doc_number] => 20230317524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-05 [patent_title] => Semiconductor Device and Method of Manufacture [patent_app_type] => utility [patent_app_number] => 18/331387 [patent_app_country] => US [patent_app_date] => 2023-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8614 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18331387 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/331387
Semiconductor device and method of manufacture Jun 7, 2023 Issued
Array ( [id] => 20540431 [patent_doc_number] => 12557520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-17 [patent_title] => Display device including a plurality of color patterns [patent_app_type] => utility [patent_app_number] => 18/206369 [patent_app_country] => US [patent_app_date] => 2023-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5901 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18206369 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/206369
Display device including a plurality of color patterns Jun 5, 2023 Issued
Array ( [id] => 19364381 [patent_doc_number] => 20240266415 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => Gate Dielectric for Gate Leakage Reduction [patent_app_type] => utility [patent_app_number] => 18/328432 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15308 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18328432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/328432
Gate dielectric for gate leakage reduction Jun 1, 2023 Issued
Array ( [id] => 19604781 [patent_doc_number] => 20240395661 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => IN-SITU MICRO-FLUIDIC CHANNELS FOR HEAT DISSIPATION IN GLASS SUBSTRATE [patent_app_type] => utility [patent_app_number] => 18/202046 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18202046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/202046
IN-SITU MICRO-FLUIDIC CHANNELS FOR HEAT DISSIPATION IN GLASS SUBSTRATE May 24, 2023 Pending
Array ( [id] => 19409114 [patent_doc_number] => 20240292625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => SEMICONDUCTOR DEVICES, FABRICATION METHODS THEREOF, 3D MEMORIES AND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/323957 [patent_app_country] => US [patent_app_date] => 2023-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18323957 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/323957
Semiconductor devices including a plurality of fins with corresponding gate oxide layers, fabrication methods thereof, 3D memories and memory devices May 24, 2023 Issued
Array ( [id] => 18812591 [patent_doc_number] => 20230386928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => Method for Forming a Stacked Transistor Device [patent_app_type] => utility [patent_app_number] => 18/322213 [patent_app_country] => US [patent_app_date] => 2023-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9927 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18322213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/322213
Method for forming a stacked transistor device May 22, 2023 Issued
Array ( [id] => 19604932 [patent_doc_number] => 20240395812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => SEMICONDUCTOR DEVICE WITH GERMANIUM-BASED CHANNEL [patent_app_type] => utility [patent_app_number] => 18/321674 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18321674 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/321674
Semiconductor device with germanium-based channel May 21, 2023 Issued
Array ( [id] => 18958884 [patent_doc_number] => 20240047211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 18/143296 [patent_app_country] => US [patent_app_date] => 2023-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18143296 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/143296
Method of manufacturing integrated circuit device May 3, 2023 Issued
Array ( [id] => 18891137 [patent_doc_number] => 11869915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Multilevel semiconductor device and structure with image sensors and wafer bonding [patent_app_type] => utility [patent_app_number] => 18/141975 [patent_app_country] => US [patent_app_date] => 2023-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 17007 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141975 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141975
Multilevel semiconductor device and structure with image sensors and wafer bonding Apr 30, 2023 Issued
Array ( [id] => 18586148 [patent_doc_number] => 20230268413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/309002 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18309002 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/309002
Pillar-shaped semiconductor device and method for manufacturing the same Apr 27, 2023 Issued
Array ( [id] => 20553005 [patent_doc_number] => 12563815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor structure having first silicide features and second silicide features and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 18/308912 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 75 [patent_no_of_words] => 8532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308912 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308912
Semiconductor structure having first silicide features and second silicide features and method for manufacturing the same Apr 27, 2023 Issued
Array ( [id] => 19138150 [patent_doc_number] => 11973126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Isolation structures for transistors [patent_app_type] => utility [patent_app_number] => 18/308213 [patent_app_country] => US [patent_app_date] => 2023-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18308213 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/308213
Isolation structures for transistors Apr 26, 2023 Issued
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