| Application number | Title of the application | Filing Date | Status |
|---|
Array
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[patent_doc_number] => 05312778
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[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Method for plasma processing using magnetically enhanced plasma chemical vapor deposition'
[patent_app_type] => 1
[patent_app_number] => 7/618142
[patent_app_country] => US
[patent_app_date] => 1990-11-23
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Array
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[id] => 3015096
[patent_doc_number] => 05326490
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Surface tension sulfuric acid composition'
[patent_app_type] => 1
[patent_app_number] => 7/602223
[patent_app_country] => US
[patent_app_date] => 1990-11-15
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[firstpage_image] =>[orig_patent_app_number] => 602223
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/602223 | Surface tension sulfuric acid composition | Nov 14, 1990 | Issued |
Array
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[id] => 2853502
[patent_doc_number] => 05112775
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-12
[patent_title] => 'Method of making diamond N-type semiconductor diamond p-n junction diode using diphosphorus pentoxide and hot filament CVD method'
[patent_app_type] => 1
[patent_app_number] => 7/609792
[patent_app_country] => US
[patent_app_date] => 1990-11-07
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[pdf_file] => patents/05/112/05112775.pdf
[firstpage_image] =>[orig_patent_app_number] => 609792
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609792 | Method of making diamond N-type semiconductor diamond p-n junction diode using diphosphorus pentoxide and hot filament CVD method | Nov 6, 1990 | Issued |
| 07/611387 | METHOD OF MANUFACTURING AN OPTOELECTRONIC DEVICE | Nov 4, 1990 | Abandoned |
Array
(
[id] => 2952399
[patent_doc_number] => 05242853
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-07
[patent_title] => 'Manufacturing process for a semiconductor device using bias ECRCVD and an etch stop layer'
[patent_app_type] => 1
[patent_app_number] => 7/603310
[patent_app_country] => US
[patent_app_date] => 1990-10-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/603310 | Manufacturing process for a semiconductor device using bias ECRCVD and an etch stop layer | Oct 24, 1990 | Issued |
Array
(
[id] => 2974118
[patent_doc_number] => 05208176
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-04
[patent_title] => 'Method of fabricating an enhanced dynamic random access memory (DRAM) cell capacitor using multiple polysilicon texturization'
[patent_app_type] => 1
[patent_app_number] => 7/603528
[patent_app_country] => US
[patent_app_date] => 1990-10-25
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| 07/602893 | METHOD FOR CONTINUOUSLY DEPOSITING A TRANSPARENT OXIDE MATERIAL BY CHEMICAL PYROLYSIS | Oct 22, 1990 | Abandoned |
Array
(
[id] => 2889683
[patent_doc_number] => 05210055
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-11
[patent_title] => 'Method for the plasma treatment of semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 7/601914
[patent_app_country] => US
[patent_app_date] => 1990-10-17
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[firstpage_image] =>[orig_patent_app_number] => 601914
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/601914 | Method for the plasma treatment of semiconductor devices | Oct 16, 1990 | Issued |
| 07/593257 | SEMICONDUCTOR DEVICE, MANUFACTURING METHOD, AND SYSTEM | Sep 30, 1990 | Abandoned |
| 07/584483 | METHOD OF FABRICATING SEMICONDUCTOR DEVICES USING AN INTERMEDIATE GRINDING STEP | Sep 16, 1990 | Abandoned |
Array
(
[id] => 2680003
[patent_doc_number] => 05066616
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Method for improving photoresist on wafers by applying fluid layer of liquid solvent'
[patent_app_type] => 1
[patent_app_number] => 7/581248
[patent_app_country] => US
[patent_app_date] => 1990-09-07
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[pdf_file] => patents/05/066/05066616.pdf
[firstpage_image] =>[orig_patent_app_number] => 581248
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/581248 | Method for improving photoresist on wafers by applying fluid layer of liquid solvent | Sep 6, 1990 | Issued |
Array
(
[id] => 2903389
[patent_doc_number] => 05248631
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'Doping of IIB-VIA semiconductors during molecular beam epitaxy using neutral free radicals'
[patent_app_type] => 1
[patent_app_number] => 7/573428
[patent_app_country] => US
[patent_app_date] => 1990-08-24
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/573428 | Doping of IIB-VIA semiconductors during molecular beam epitaxy using neutral free radicals | Aug 23, 1990 | Issued |
| 07/569487 | REDUCED SIZE ETCHING METHOD FOR INTEGRATED CIRCUITS | Aug 15, 1990 | Abandoned |
| 07/568388 | PLASMA ETCH SYSTEM | Aug 15, 1990 | Abandoned |
Array
(
[id] => 2743411
[patent_doc_number] => 05002896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-26
[patent_title] => 'Mask-ROM manufacturing method that enhances integration density'
[patent_app_type] => 1
[patent_app_number] => 7/567797
[patent_app_country] => US
[patent_app_date] => 1990-08-15
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[pdf_file] => patents/05/002/05002896.pdf
[firstpage_image] =>[orig_patent_app_number] => 567797
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/567797 | Mask-ROM manufacturing method that enhances integration density | Aug 14, 1990 | Issued |
Array
(
[id] => 2679980
[patent_doc_number] => 05066615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-19
[patent_title] => 'Photolithographic processes using thin coatings of refractory metal silicon nitrides as antireflection layers'
[patent_app_type] => 1
[patent_app_number] => 7/562874
[patent_app_country] => US
[patent_app_date] => 1990-08-06
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 07/562874 | Photolithographic processes using thin coatings of refractory metal silicon nitrides as antireflection layers | Aug 5, 1990 | Issued |
| 07/561768 | SOLUBLE OXIDES FOR INTEGRATED CIRCUIT FABRICATION FORMED BY THE INCOMPLETE DISSOCIATION OF THE PRECURSOR GAS | Aug 1, 1990 | Abandoned |
| 07/562411 | GETTERING TREATMENT PROCESS | Jul 31, 1990 | Abandoned |
| 07/561490 | FORMING COMPLEMENTARY BIPOLAR AND MOS TRANSISTOR HAVING POWER AND LOGIC STRUCTURES ON THE SAME INTEGRATED CIRCUIT SUBSTRATE | Jul 31, 1990 | Abandoned |
| 07/560530 | VHF/UHF PLASMA PROCESS FOR USE IN FORMING INTEGRATED CIRCUIT STRUCTURES ON SEMICONDUCTOR WAFERS | Jul 30, 1990 | Abandoned |