
Ching Chang
Examiner (ID: 17036, Phone: (571)272-4857 , Office: P/3748 )
| Most Active Art Unit | 3748 |
| Art Unit(s) | 3748, 3746 |
| Total Applications | 1871 |
| Issued Applications | 1700 |
| Pending Applications | 11 |
| Abandoned Applications | 170 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3078882
[patent_doc_number] => 05322974
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-21
[patent_title] => 'Interleaved fine line cables'
[patent_app_type] => 1
[patent_app_number] => 7/937010
[patent_app_country] => US
[patent_app_date] => 1992-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 2694
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/322/05322974.pdf
[firstpage_image] =>[orig_patent_app_number] => 937010
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/937010 | Interleaved fine line cables | Aug 30, 1992 | Issued |
Array
(
[id] => 2895196
[patent_doc_number] => 05270487
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-14
[patent_title] => 'Grommet'
[patent_app_type] => 1
[patent_app_number] => 7/936315
[patent_app_country] => US
[patent_app_date] => 1992-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 3565
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/270/05270487.pdf
[firstpage_image] =>[orig_patent_app_number] => 936315
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/936315 | Grommet | Aug 27, 1992 | Issued |
Array
(
[id] => 3066955
[patent_doc_number] => 05310965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-10
[patent_title] => 'Multi-level wiring structure having an organic interlayer insulating film'
[patent_app_type] => 1
[patent_app_number] => 7/936300
[patent_app_country] => US
[patent_app_date] => 1992-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 4494
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/310/05310965.pdf
[firstpage_image] =>[orig_patent_app_number] => 936300
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/936300 | Multi-level wiring structure having an organic interlayer insulating film | Aug 27, 1992 | Issued |
Array
(
[id] => 3414978
[patent_doc_number] => 05444186
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'Multilayer conductive wire for semiconductor device and manufacturing method thereof'
[patent_app_type] => 1
[patent_app_number] => 7/933633
[patent_app_country] => US
[patent_app_date] => 1992-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 37
[patent_no_of_words] => 7026
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/444/05444186.pdf
[firstpage_image] =>[orig_patent_app_number] => 933633
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/933633 | Multilayer conductive wire for semiconductor device and manufacturing method thereof | Aug 23, 1992 | Issued |
Array
(
[id] => 2993817
[patent_doc_number] => 05347091
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Multilayer circuit card connector'
[patent_app_type] => 1
[patent_app_number] => 7/933424
[patent_app_country] => US
[patent_app_date] => 1992-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1397
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 244
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/347/05347091.pdf
[firstpage_image] =>[orig_patent_app_number] => 933424
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/933424 | Multilayer circuit card connector | Aug 20, 1992 | Issued |
Array
(
[id] => 3086315
[patent_doc_number] => 05280139
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Selectively releasing conductive runner and substrate assembly'
[patent_app_type] => 1
[patent_app_number] => 7/930498
[patent_app_country] => US
[patent_app_date] => 1992-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 11
[patent_no_of_words] => 1490
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/280/05280139.pdf
[firstpage_image] =>[orig_patent_app_number] => 930498
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/930498 | Selectively releasing conductive runner and substrate assembly | Aug 16, 1992 | Issued |
| 07/929721 | SPECIAL INTERCONNECT LAYER FOR ADVANCED MULTI-CHIP MODULE PACKAGES | Aug 12, 1992 | Abandoned |
Array
(
[id] => 3053292
[patent_doc_number] => 05324892
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-28
[patent_title] => 'Method of fabricating an electronic interconnection'
[patent_app_type] => 1
[patent_app_number] => 7/926494
[patent_app_country] => US
[patent_app_date] => 1992-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2982
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/324/05324892.pdf
[firstpage_image] =>[orig_patent_app_number] => 926494
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/926494 | Method of fabricating an electronic interconnection | Aug 6, 1992 | Issued |
Array
(
[id] => 3099278
[patent_doc_number] => 05293006
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-08
[patent_title] => 'Solder bump including circular lip'
[patent_app_type] => 1
[patent_app_number] => 7/927069
[patent_app_country] => US
[patent_app_date] => 1992-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 3513
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/293/05293006.pdf
[firstpage_image] =>[orig_patent_app_number] => 927069
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/927069 | Solder bump including circular lip | Aug 6, 1992 | Issued |
| 07/921539 | MLC CONDUCTOR PATTERN OFF-SET DESIGN TO ELIMINATE LINE TO VIA CRACKING | Jul 28, 1992 | Abandoned |
Array
(
[id] => 3015846
[patent_doc_number] => 05308929
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-03
[patent_title] => 'Via hole structure and process for formation thereof'
[patent_app_type] => 1
[patent_app_number] => 7/919909
[patent_app_country] => US
[patent_app_date] => 1992-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 23
[patent_no_of_words] => 3996
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/308/05308929.pdf
[firstpage_image] =>[orig_patent_app_number] => 919909
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/919909 | Via hole structure and process for formation thereof | Jul 26, 1992 | Issued |
Array
(
[id] => 3098517
[patent_doc_number] => 05298685
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Interconnection method and structure for organic circuit boards'
[patent_app_type] => 1
[patent_app_number] => 7/913086
[patent_app_country] => US
[patent_app_date] => 1992-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2961
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/298/05298685.pdf
[firstpage_image] =>[orig_patent_app_number] => 913086
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/913086 | Interconnection method and structure for organic circuit boards | Jul 13, 1992 | Issued |
Array
(
[id] => 3099713
[patent_doc_number] => 05319158
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-06-07
[patent_title] => 'Coil integrated semi-conductor device and method of making the same'
[patent_app_type] => 1
[patent_app_number] => 7/912143
[patent_app_country] => US
[patent_app_date] => 1992-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 3510
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/319/05319158.pdf
[firstpage_image] =>[orig_patent_app_number] => 912143
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/912143 | Coil integrated semi-conductor device and method of making the same | Jul 9, 1992 | Issued |
Array
(
[id] => 3102517
[patent_doc_number] => 05315070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Printed wiring board to which solder has been applied'
[patent_app_type] => 1
[patent_app_number] => 7/905474
[patent_app_country] => US
[patent_app_date] => 1992-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2216
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/315/05315070.pdf
[firstpage_image] =>[orig_patent_app_number] => 905474
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/905474 | Printed wiring board to which solder has been applied | Jun 28, 1992 | Issued |
Array
(
[id] => 3015870
[patent_doc_number] => 05332868
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-26
[patent_title] => 'Method and structure for suppressing stress-induced defects in integrated circuit conductive lines'
[patent_app_type] => 1
[patent_app_number] => 7/902182
[patent_app_country] => US
[patent_app_date] => 1992-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3639
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/332/05332868.pdf
[firstpage_image] =>[orig_patent_app_number] => 902182
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/902182 | Method and structure for suppressing stress-induced defects in integrated circuit conductive lines | Jun 21, 1992 | Issued |
Array
(
[id] => 3018368
[patent_doc_number] => 05340947
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-23
[patent_title] => 'Ceramic substrates with highly conductive metal vias'
[patent_app_type] => 1
[patent_app_number] => 7/902082
[patent_app_country] => US
[patent_app_date] => 1992-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 12
[patent_no_of_words] => 4117
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/340/05340947.pdf
[firstpage_image] =>[orig_patent_app_number] => 902082
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/902082 | Ceramic substrates with highly conductive metal vias | Jun 21, 1992 | Issued |
Array
(
[id] => 3098499
[patent_doc_number] => 05298684
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-29
[patent_title] => 'Circuit board having a lateral conductive pattern and shielded regions as well as a method of manufacturing such a board'
[patent_app_type] => 1
[patent_app_number] => 7/897829
[patent_app_country] => US
[patent_app_date] => 1992-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 17
[patent_no_of_words] => 4045
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/298/05298684.pdf
[firstpage_image] =>[orig_patent_app_number] => 897829
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/897829 | Circuit board having a lateral conductive pattern and shielded regions as well as a method of manufacturing such a board | Jun 11, 1992 | Issued |
Array
(
[id] => 3053621
[patent_doc_number] => 05306873
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'Load cell with strain gauges having low temperature dependent coefficient of resistance'
[patent_app_type] => 1
[patent_app_number] => 7/859418
[patent_app_country] => US
[patent_app_date] => 1992-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3788
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/306/05306873.pdf
[firstpage_image] =>[orig_patent_app_number] => 859418
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/859418 | Load cell with strain gauges having low temperature dependent coefficient of resistance | May 26, 1992 | Issued |
Array
(
[id] => 2981529
[patent_doc_number] => 05252784
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Electronic-parts mounting board and electronic-parts mounting board frame'
[patent_app_type] => 1
[patent_app_number] => 7/888812
[patent_app_country] => US
[patent_app_date] => 1992-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 25
[patent_no_of_words] => 8232
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/252/05252784.pdf
[firstpage_image] =>[orig_patent_app_number] => 888812
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/888812 | Electronic-parts mounting board and electronic-parts mounting board frame | May 26, 1992 | Issued |
Array
(
[id] => 2923925
[patent_doc_number] => 05235140
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Electrode bump for flip chip die attachment'
[patent_app_type] => 1
[patent_app_number] => 7/886585
[patent_app_country] => US
[patent_app_date] => 1992-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 1712
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/235/05235140.pdf
[firstpage_image] =>[orig_patent_app_number] => 886585
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/886585 | Electrode bump for flip chip die attachment | May 20, 1992 | Issued |