
Chris C. Chu
Examiner (ID: 11212)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 1003 |
| Issued Applications | 778 |
| Pending Applications | 1 |
| Abandoned Applications | 227 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4756713
[patent_doc_number] => 20080308938
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-12-18
[patent_title] => 'Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure'
[patent_app_type] => utility
[patent_app_number] => 12/149861
[patent_app_country] => US
[patent_app_date] => 2008-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3002
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0308/20080308938.pdf
[firstpage_image] =>[orig_patent_app_number] => 12149861
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/149861 | Under bump metallurgy structure and wafer structure using the same and method of manufacturing wafer structure | May 8, 2008 | Issued |
Array
(
[id] => 4511081
[patent_doc_number] => 07915742
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-29
[patent_title] => 'Determining the placement of semiconductor components on an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/111536
[patent_app_country] => US
[patent_app_date] => 2008-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 4815
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/915/07915742.pdf
[firstpage_image] =>[orig_patent_app_number] => 12111536
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/111536 | Determining the placement of semiconductor components on an integrated circuit | Apr 28, 2008 | Issued |
Array
(
[id] => 326519
[patent_doc_number] => 07514290
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-04-07
[patent_title] => 'Chip-to-wafer integration technology for three-dimensional chip stacking'
[patent_app_type] => utility
[patent_app_number] => 12/108512
[patent_app_country] => US
[patent_app_date] => 2008-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1748
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 322
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/514/07514290.pdf
[firstpage_image] =>[orig_patent_app_number] => 12108512
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/108512 | Chip-to-wafer integration technology for three-dimensional chip stacking | Apr 23, 2008 | Issued |
Array
(
[id] => 4856540
[patent_doc_number] => 20080265390
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-30
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/107795
[patent_app_country] => US
[patent_app_date] => 2008-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5952
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0265/20080265390.pdf
[firstpage_image] =>[orig_patent_app_number] => 12107795
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/107795 | Semiconductor device | Apr 22, 2008 | Issued |
Array
(
[id] => 14520
[patent_doc_number] => 07808100
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-05
[patent_title] => 'Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element'
[patent_app_type] => utility
[patent_app_number] => 12/106486
[patent_app_country] => US
[patent_app_date] => 2008-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 7172
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/808/07808100.pdf
[firstpage_image] =>[orig_patent_app_number] => 12106486
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/106486 | Power semiconductor module with pressure element and method for fabricating a power semiconductor module with a pressure element | Apr 20, 2008 | Issued |
Array
(
[id] => 5001
[patent_doc_number] => 07816676
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-19
[patent_title] => 'Hermetically sealed package and methods of making the same'
[patent_app_type] => utility
[patent_app_number] => 12/062364
[patent_app_country] => US
[patent_app_date] => 2008-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 7150
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/816/07816676.pdf
[firstpage_image] =>[orig_patent_app_number] => 12062364
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/062364 | Hermetically sealed package and methods of making the same | Apr 2, 2008 | Issued |
Array
(
[id] => 5469875
[patent_doc_number] => 20090243041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-10-01
[patent_title] => 'Semiconductor Devices and Methods of Manufacture Thereof'
[patent_app_type] => utility
[patent_app_number] => 12/060626
[patent_app_country] => US
[patent_app_date] => 2008-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7531
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0243/20090243041.pdf
[firstpage_image] =>[orig_patent_app_number] => 12060626
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/060626 | Semiconductor devices and methods of manufacture thereof | Mar 31, 2008 | Issued |
Array
(
[id] => 9504284
[patent_doc_number] => 08742602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-03
[patent_title] => 'Vertical electrical interconnect formed on support prior to die mount'
[patent_app_type] => utility
[patent_app_number] => 12/046651
[patent_app_country] => US
[patent_app_date] => 2008-03-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 4472
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12046651
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/046651 | Vertical electrical interconnect formed on support prior to die mount | Mar 11, 2008 | Issued |
Array
(
[id] => 24943
[patent_doc_number] => 07795700
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-14
[patent_title] => 'Inductively coupled integrated circuit with magnetic communication path and methods for use therewith'
[patent_app_type] => utility
[patent_app_number] => 12/039256
[patent_app_country] => US
[patent_app_date] => 2008-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 76
[patent_no_of_words] => 29539
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/795/07795700.pdf
[firstpage_image] =>[orig_patent_app_number] => 12039256
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/039256 | Inductively coupled integrated circuit with magnetic communication path and methods for use therewith | Feb 27, 2008 | Issued |
Array
(
[id] => 8294935
[patent_doc_number] => 08222724
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-07-17
[patent_title] => 'Semiconductor element module and method for manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/866322
[patent_app_country] => US
[patent_app_date] => 2008-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 13814
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12866322
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/866322 | Semiconductor element module and method for manufacturing the same | Feb 13, 2008 | Issued |
Array
(
[id] => 7763634
[patent_doc_number] => 08115304
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-02-14
[patent_title] => 'Method of implementing a discrete element in an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/027251
[patent_app_country] => US
[patent_app_date] => 2008-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 3943
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/115/08115304.pdf
[firstpage_image] =>[orig_patent_app_number] => 12027251
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/027251 | Method of implementing a discrete element in an integrated circuit | Feb 5, 2008 | Issued |
Array
(
[id] => 7551140
[patent_doc_number] => 08063474
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Embedded die package on package (POP) with pre-molded leadframe'
[patent_app_type] => utility
[patent_app_number] => 12/026742
[patent_app_country] => US
[patent_app_date] => 2008-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 43
[patent_no_of_words] => 2627
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 191
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/063/08063474.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026742
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026742 | Embedded die package on package (POP) with pre-molded leadframe | Feb 5, 2008 | Issued |
Array
(
[id] => 45191
[patent_doc_number] => 07777330
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-17
[patent_title] => 'High bandwidth cache-to-processing unit communication in a multiple processor/cache system'
[patent_app_type] => utility
[patent_app_number] => 12/026325
[patent_app_country] => US
[patent_app_date] => 2008-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5486
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/777/07777330.pdf
[firstpage_image] =>[orig_patent_app_number] => 12026325
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/026325 | High bandwidth cache-to-processing unit communication in a multiple processor/cache system | Feb 4, 2008 | Issued |
Array
(
[id] => 4527118
[patent_doc_number] => 07952210
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-31
[patent_title] => 'Semiconductor package and fabrication method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/023761
[patent_app_country] => US
[patent_app_date] => 2008-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 31
[patent_no_of_words] => 4657
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/952/07952210.pdf
[firstpage_image] =>[orig_patent_app_number] => 12023761
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/023761 | Semiconductor package and fabrication method thereof | Jan 30, 2008 | Issued |
Array
(
[id] => 23392
[patent_doc_number] => 07800239
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-21
[patent_title] => 'Thick metal interconnect with metal pad caps at selective sites and process for making the same'
[patent_app_type] => utility
[patent_app_number] => 12/012121
[patent_app_country] => US
[patent_app_date] => 2008-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 22
[patent_no_of_words] => 7702
[patent_no_of_claims] => 40
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/800/07800239.pdf
[firstpage_image] =>[orig_patent_app_number] => 12012121
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/012121 | Thick metal interconnect with metal pad caps at selective sites and process for making the same | Jan 30, 2008 | Issued |
Array
(
[id] => 5542223
[patent_doc_number] => 20090152100
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Thick metal interconnect with metal pad caps at selective sites and process for making the same'
[patent_app_type] => utility
[patent_app_number] => 12/012120
[patent_app_country] => US
[patent_app_date] => 2008-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8041
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20090152100.pdf
[firstpage_image] =>[orig_patent_app_number] => 12012120
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/012120 | Thick metal interconnect with metal pad caps at selective sites and process for making the same | Jan 30, 2008 | Issued |
Array
(
[id] => 5377459
[patent_doc_number] => 20090189298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-30
[patent_title] => 'Bonding pad structure and debug method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/010571
[patent_app_country] => US
[patent_app_date] => 2008-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 1469
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0189/20090189298.pdf
[firstpage_image] =>[orig_patent_app_number] => 12010571
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/010571 | Bonding pad structure and debug method thereof | Jan 27, 2008 | Abandoned |
Array
(
[id] => 9590036
[patent_doc_number] => 08779580
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-07-15
[patent_title] => 'Electronic component package and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/010321
[patent_app_country] => US
[patent_app_date] => 2008-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 2495
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12010321
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/010321 | Electronic component package and manufacturing method thereof | Jan 22, 2008 | Issued |
Array
(
[id] => 4825873
[patent_doc_number] => 20080124837
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'Method of mounting semiconductor chip to circuit substrate using solder bumps and dummy bumps'
[patent_app_type] => utility
[patent_app_number] => 12/007933
[patent_app_country] => US
[patent_app_date] => 2008-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3515
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20080124837.pdf
[firstpage_image] =>[orig_patent_app_number] => 12007933
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/007933 | Method of mounting semiconductor chip to circuit substrate using solder bumps and dummy bumps | Jan 16, 2008 | Issued |
Array
(
[id] => 8329171
[patent_doc_number] => 08237266
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Component stacking for integrated circuit electronic package'
[patent_app_type] => utility
[patent_app_number] => 12/015122
[patent_app_country] => US
[patent_app_date] => 2008-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3211
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12015122
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/015122 | Component stacking for integrated circuit electronic package | Jan 15, 2008 | Issued |