Search

Chris C. Chu

Examiner (ID: 11832)

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
1003
Issued Applications
778
Pending Applications
1
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1419738 [patent_doc_number] => 06525425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Copper interconnects with improved electromigration resistance and low resistivity' [patent_app_type] => B1 [patent_app_number] => 09/593231 [patent_app_country] => US [patent_app_date] => 2000-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3552 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525425.pdf [firstpage_image] =>[orig_patent_app_number] => 09593231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/593231
Copper interconnects with improved electromigration resistance and low resistivity Jun 13, 2000 Issued
Array ( [id] => 1207141 [patent_doc_number] => 06717245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-06 [patent_title] => 'Chip scale packages performed by wafer level processing' [patent_app_type] => B1 [patent_app_number] => 09/586243 [patent_app_country] => US [patent_app_date] => 2000-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 14 [patent_no_of_words] => 5817 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/717/06717245.pdf [firstpage_image] =>[orig_patent_app_number] => 09586243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586243
Chip scale packages performed by wafer level processing Jun 1, 2000 Issued
Array ( [id] => 539189 [patent_doc_number] => 07173339 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-06 [patent_title] => 'Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure' [patent_app_type] => utility [patent_app_number] => 09/585682 [patent_app_country] => US [patent_app_date] => 2000-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4432 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173339.pdf [firstpage_image] =>[orig_patent_app_number] => 09585682 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/585682
Semiconductor device having a substrate an undoped silicon oxide structure and an overlaying doped silicon oxide structure with a sidewall terminating at the undoped silicon oxide structure May 31, 2000 Issued
Array ( [id] => 1241554 [patent_doc_number] => 06683377 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Multi-stacked memory package' [patent_app_type] => B1 [patent_app_number] => 09/583183 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2832 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683377.pdf [firstpage_image] =>[orig_patent_app_number] => 09583183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/583183
Multi-stacked memory package May 29, 2000 Issued
Array ( [id] => 651311 [patent_doc_number] => 07112889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-09-26 [patent_title] => 'Semiconductor device having an alignment mark formed by the same material with a metal post' [patent_app_type] => utility [patent_app_number] => 09/577932 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 57 [patent_no_of_words] => 11797 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112889.pdf [firstpage_image] =>[orig_patent_app_number] => 09577932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/577932
Semiconductor device having an alignment mark formed by the same material with a metal post May 24, 2000 Issued
Array ( [id] => 1074093 [patent_doc_number] => 06838758 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-04 [patent_title] => 'Package and method for making an underfilled integrated circuit' [patent_app_type] => utility [patent_app_number] => 09/567533 [patent_app_country] => US [patent_app_date] => 2000-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3838 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/838/06838758.pdf [firstpage_image] =>[orig_patent_app_number] => 09567533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/567533
Package and method for making an underfilled integrated circuit May 9, 2000 Issued
Array ( [id] => 7645242 [patent_doc_number] => 06472730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/551741 [patent_app_country] => US [patent_app_date] => 2000-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9156 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472730.pdf [firstpage_image] =>[orig_patent_app_number] => 09551741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/551741
Semiconductor device and method of manufacturing the same Apr 17, 2000 Issued
Array ( [id] => 6158074 [patent_doc_number] => 20020146897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'STRUCTURE HAVING REDUCED LATERAL SPACER EROSION' [patent_app_type] => new [patent_app_number] => 09/540610 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8188 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20020146897.pdf [firstpage_image] =>[orig_patent_app_number] => 09540610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/540610
Structure having reduced lateral spacer erosion Mar 30, 2000 Issued
Array ( [id] => 1132571 [patent_doc_number] => 06787900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Semiconductor module and insulating substrate thereof' [patent_app_type] => B2 [patent_app_number] => 09/534043 [patent_app_country] => US [patent_app_date] => 2000-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4418 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787900.pdf [firstpage_image] =>[orig_patent_app_number] => 09534043 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/534043
Semiconductor module and insulating substrate thereof Mar 23, 2000 Issued
Array ( [id] => 1480611 [patent_doc_number] => 06452255 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Low inductance leadless package' [patent_app_type] => B1 [patent_app_number] => 09/528662 [patent_app_country] => US [patent_app_date] => 2000-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 4138 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452255.pdf [firstpage_image] =>[orig_patent_app_number] => 09528662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/528662
Low inductance leadless package Mar 19, 2000 Issued
Array ( [id] => 1385116 [patent_doc_number] => 06559548 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Wiring structure of semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/527222 [patent_app_country] => US [patent_app_date] => 2000-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 45 [patent_no_of_words] => 6855 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559548.pdf [firstpage_image] =>[orig_patent_app_number] => 09527222 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/527222
Wiring structure of semiconductor device Mar 15, 2000 Issued
09/495300 Semiconductor device and manufacturing method thereof Jan 31, 2000 Abandoned
Array ( [id] => 6772468 [patent_doc_number] => 20030015806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Semiconductor wafer' [patent_app_type] => new [patent_app_number] => 09/492761 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7755 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20030015806.pdf [firstpage_image] =>[orig_patent_app_number] => 09492761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492761
Semiconductor wafer Jan 26, 2000 Issued
Array ( [id] => 1547595 [patent_doc_number] => 06445071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Semiconductor device having an improved multi-layer interconnection structure and manufacturing method thereof' [patent_app_type] => B1 [patent_app_number] => 09/488781 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3283 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445071.pdf [firstpage_image] =>[orig_patent_app_number] => 09488781 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488781
Semiconductor device having an improved multi-layer interconnection structure and manufacturing method thereof Jan 20, 2000 Issued
09/475002 METAL STUD ARRAY PACKAGING Dec 29, 1999 Abandoned
Array ( [id] => 6671930 [patent_doc_number] => 20030057533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'AMORPHOUS SILICON SENSOR WITH MICRO-SPRING INTERCONNECTS FOR ACHIEVING HIGH UNIFORMITY IN INTEGRATED LIGHT-EMITTING SOURCES' [patent_app_type] => new [patent_app_number] => 09/469122 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8735 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20030057533.pdf [firstpage_image] =>[orig_patent_app_number] => 09469122 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/469122
Amorphous silicon sensor with micro-spring interconnects for achieving high uniformity in integrated light-emitting sources Dec 20, 1999 Issued
Array ( [id] => 6349120 [patent_doc_number] => 20020056909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'SEMICONDUCTOR CHIP PACKAGE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => new [patent_app_number] => 09/464322 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0056/20020056909.pdf [firstpage_image] =>[orig_patent_app_number] => 09464322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464322
SEMICONDUCTOR CHIP PACKAGE AND METHOD OF FABRICATING THE SAME Dec 14, 1999 Abandoned
Array ( [id] => 6300606 [patent_doc_number] => 20020093089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-18 [patent_title] => 'COMPLIANT MOUNTING INTERFACE FOR ELECTRONIC DEVICES' [patent_app_type] => new [patent_app_number] => 09/452833 [patent_app_country] => US [patent_app_date] => 1999-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3298 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20020093089.pdf [firstpage_image] =>[orig_patent_app_number] => 09452833 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452833
COMPLIANT MOUNTING INTERFACE FOR ELECTRONIC DEVICES Nov 30, 1999 Abandoned
Array ( [id] => 1478896 [patent_doc_number] => 06344686 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Power electronic component including cooling means' [patent_app_type] => B1 [patent_app_number] => 09/447832 [patent_app_country] => US [patent_app_date] => 1999-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2679 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/344/06344686.pdf [firstpage_image] =>[orig_patent_app_number] => 09447832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447832
Power electronic component including cooling means Nov 22, 1999 Issued
Array ( [id] => 1424695 [patent_doc_number] => 06507113 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Electronic interface structures and methods of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/443410 [patent_app_country] => US [patent_app_date] => 1999-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4571 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507113.pdf [firstpage_image] =>[orig_patent_app_number] => 09443410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/443410
Electronic interface structures and methods of fabrication Nov 18, 1999 Issued
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