
Chris C. Chu
Examiner (ID: 19280)
| Most Active Art Unit | 2815 |
| Art Unit(s) | 2815 |
| Total Applications | 1003 |
| Issued Applications | 778 |
| Pending Applications | 1 |
| Abandoned Applications | 227 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
| 13/448631 | STACKED SEMICONDUCTOR PACKAGE THAT PREVENTS DAMAGE TO SEMICONDUCTOR CHIP WHEN WIRE-BONDING AND METHOD FOR MANUFACTURING THE SAME | Apr 16, 2012 | Abandoned |
Array
(
[id] => 9273976
[patent_doc_number] => 08637909
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-01-28
[patent_title] => 'Mixed mode dual switch'
[patent_app_type] => utility
[patent_app_number] => 13/442313
[patent_app_country] => US
[patent_app_date] => 2012-04-09
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/442313 | Mixed mode dual switch | Apr 8, 2012 | Issued |
Array
(
[id] => 8743865
[patent_doc_number] => 20130083582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-04
[patent_title] => 'STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/439286
[patent_app_country] => US
[patent_app_date] => 2012-04-04
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/439286 | Stub minimization for assemblies without wirebonds to package substrate | Apr 3, 2012 | Issued |
Array
(
[id] => 9216762
[patent_doc_number] => 08629565
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-14
[patent_title] => 'Thin wafer protection device'
[patent_app_type] => utility
[patent_app_number] => 13/419078
[patent_app_country] => US
[patent_app_date] => 2012-03-13
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/419078 | Thin wafer protection device | Mar 12, 2012 | Issued |
Array
(
[id] => 8333255
[patent_doc_number] => 20120199951
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-09
[patent_title] => 'INTEGRATED SHUNT RESISTOR WITH EXTERNAL CONTACT IN A SEMICONDUCTOR PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/412347
[patent_app_country] => US
[patent_app_date] => 2012-03-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/412347 | Integrated shunt resistor with external contact in a semiconductor package | Mar 4, 2012 | Issued |
Array
(
[id] => 9216760
[patent_doc_number] => 08629563
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-01-14
[patent_title] => 'Method for packaging semiconductor dies having through-silicon vias'
[patent_app_type] => utility
[patent_app_number] => 13/368999
[patent_app_country] => US
[patent_app_date] => 2012-02-08
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/368999 | Method for packaging semiconductor dies having through-silicon vias | Feb 7, 2012 | Issued |
Array
(
[id] => 9113632
[patent_doc_number] => 08569811
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-10-29
[patent_title] => 'Self clamping FET devices in circuits using transient sources'
[patent_app_type] => utility
[patent_app_number] => 13/364258
[patent_app_country] => US
[patent_app_date] => 2012-02-01
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/364258 | Self clamping FET devices in circuits using transient sources | Jan 31, 2012 | Issued |
Array
(
[id] => 8321326
[patent_doc_number] => 20120193737
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-08-02
[patent_title] => 'MRAM DEVICE AND METHOD OF ASSEMBLING SAME'
[patent_app_type] => utility
[patent_app_number] => 13/333996
[patent_app_country] => US
[patent_app_date] => 2011-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333996
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/333996 | MRAM DEVICE AND METHOD OF ASSEMBLING SAME | Dec 20, 2011 | Abandoned |
Array
(
[id] => 9763052
[patent_doc_number] => 08847381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-30
[patent_title] => 'Semiconductor element housing package and semiconductor device equipped with the same'
[patent_app_type] => utility
[patent_app_number] => 13/980440
[patent_app_country] => US
[patent_app_date] => 2011-12-19
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/980440 | Semiconductor element housing package and semiconductor device equipped with the same | Dec 18, 2011 | Issued |
Array
(
[id] => 7818091
[patent_doc_number] => 20120064711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'COPPER BONDING COMPATIBLE BOND PAD STRUCTURE AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/298455
[patent_app_country] => US
[patent_app_date] => 2011-11-17
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 13298455
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/298455 | Copper bonding compatible bond pad structure and method | Nov 16, 2011 | Issued |
Array
(
[id] => 7767216
[patent_doc_number] => 20120034741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-09
[patent_title] => 'POWER DEVICE PACKAGE COMPRISING METAL TAB DIE ATTACH PADDLE (DAP) AND METHOD OF FABRICATING THE PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 13/278664
[patent_app_country] => US
[patent_app_date] => 2011-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0034/20120034741.pdf
[firstpage_image] =>[orig_patent_app_number] => 13278664
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/278664 | Power device package comprising metal tab die attach paddle (DAP) and method of fabricating the package | Oct 20, 2011 | Issued |
Array
(
[id] => 7767215
[patent_doc_number] => 20120034740
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-09
[patent_title] => 'PRE-ENCAPSULATED CAVITY INTERPOSER'
[patent_app_type] => utility
[patent_app_number] => 13/277988
[patent_app_country] => US
[patent_app_date] => 2011-10-20
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 13277988
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/277988 | Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages | Oct 19, 2011 | Issued |
Array
(
[id] => 8689811
[patent_doc_number] => 08389338
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-05
[patent_title] => 'Embedded die package on package (POP) with pre-molded leadframe'
[patent_app_type] => utility
[patent_app_number] => 13/276372
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/276372 | Embedded die package on package (POP) with pre-molded leadframe | Oct 18, 2011 | Issued |
Array
(
[id] => 7762801
[patent_doc_number] => 20120032325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-02-09
[patent_title] => 'SEMICONDUCTOR DEVICE'
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[firstpage_image] =>[orig_patent_app_number] => 13274738
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/274738 | Semiconductor device | Oct 16, 2011 | Issued |
Array
(
[id] => 8127633
[patent_doc_number] => 20120088363
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[patent_kind] => A1
[patent_issue_date] => 2012-04-12
[patent_title] => 'METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION'
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[patent_app_number] => 13/269538
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[firstpage_image] =>[orig_patent_app_number] => 13269538
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/269538 | Method and system for forming conductive bumping with copper interconnection | Oct 6, 2011 | Issued |
Array
(
[id] => 7750586
[patent_doc_number] => 20120025372
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[patent_kind] => A1
[patent_issue_date] => 2012-02-02
[patent_title] => 'CHIP HAVING A DRIVING INTEGRATED CIRCUIT'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/253076 | Chip having a driving integrated circuit | Oct 4, 2011 | Issued |
Array
(
[id] => 8249165
[patent_doc_number] => 20120153489
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-06-21
[patent_title] => 'SEMICONDUCTOR PACKAGE HAVING PROXIMITY COMMUNICATION SIGNAL INPUT TERMINALS AND MANUFACTURING METHODS THEREOF'
[patent_app_type] => utility
[patent_app_number] => 13/252850
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[patent_app_date] => 2011-10-04
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[pdf_file] => publications/A1/0153/20120153489.pdf
[firstpage_image] =>[orig_patent_app_number] => 13252850
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/252850 | Semiconductor package having proximity communication signal input terminals and manufacturing methods thereof | Oct 3, 2011 | Issued |
Array
(
[id] => 8742690
[patent_doc_number] => 20130082407
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[patent_issue_date] => 2013-04-04
[patent_title] => 'Integrated Circuit Package And Method'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/252833 | Integrated Circuit Package And Method | Oct 3, 2011 | Abandoned |
Array
(
[id] => 8742668
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/251498 | Die having coefficient of thermal expansion graded layer | Oct 2, 2011 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/251846 | Self-aligning structures and method for integrated chips | Oct 2, 2011 | Issued |