Search

Chris C. Chu

Examiner (ID: 19280)

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
1003
Issued Applications
778
Pending Applications
1
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
13/448631 STACKED SEMICONDUCTOR PACKAGE THAT PREVENTS DAMAGE TO SEMICONDUCTOR CHIP WHEN WIRE-BONDING AND METHOD FOR MANUFACTURING THE SAME Apr 16, 2012 Abandoned
Array ( [id] => 9273976 [patent_doc_number] => 08637909 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-28 [patent_title] => 'Mixed mode dual switch' [patent_app_type] => utility [patent_app_number] => 13/442313 [patent_app_country] => US [patent_app_date] => 2012-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7256 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442313 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/442313
Mixed mode dual switch Apr 8, 2012 Issued
Array ( [id] => 8743865 [patent_doc_number] => 20130083582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'STUB MINIMIZATION FOR ASSEMBLIES WITHOUT WIREBONDS TO PACKAGE SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/439286 [patent_app_country] => US [patent_app_date] => 2012-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16177 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13439286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/439286
Stub minimization for assemblies without wirebonds to package substrate Apr 3, 2012 Issued
Array ( [id] => 9216762 [patent_doc_number] => 08629565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Thin wafer protection device' [patent_app_type] => utility [patent_app_number] => 13/419078 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 1875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419078 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419078
Thin wafer protection device Mar 12, 2012 Issued
Array ( [id] => 8333255 [patent_doc_number] => 20120199951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'INTEGRATED SHUNT RESISTOR WITH EXTERNAL CONTACT IN A SEMICONDUCTOR PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/412347 [patent_app_country] => US [patent_app_date] => 2012-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6343 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13412347 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/412347
Integrated shunt resistor with external contact in a semiconductor package Mar 4, 2012 Issued
Array ( [id] => 9216760 [patent_doc_number] => 08629563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Method for packaging semiconductor dies having through-silicon vias' [patent_app_type] => utility [patent_app_number] => 13/368999 [patent_app_country] => US [patent_app_date] => 2012-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368999 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/368999
Method for packaging semiconductor dies having through-silicon vias Feb 7, 2012 Issued
Array ( [id] => 9113632 [patent_doc_number] => 08569811 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-29 [patent_title] => 'Self clamping FET devices in circuits using transient sources' [patent_app_type] => utility [patent_app_number] => 13/364258 [patent_app_country] => US [patent_app_date] => 2012-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5168 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13364258 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/364258
Self clamping FET devices in circuits using transient sources Jan 31, 2012 Issued
Array ( [id] => 8321326 [patent_doc_number] => 20120193737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'MRAM DEVICE AND METHOD OF ASSEMBLING SAME' [patent_app_type] => utility [patent_app_number] => 13/333996 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2696 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13333996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/333996
MRAM DEVICE AND METHOD OF ASSEMBLING SAME Dec 20, 2011 Abandoned
Array ( [id] => 9763052 [patent_doc_number] => 08847381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Semiconductor element housing package and semiconductor device equipped with the same' [patent_app_type] => utility [patent_app_number] => 13/980440 [patent_app_country] => US [patent_app_date] => 2011-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7216 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13980440 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/980440
Semiconductor element housing package and semiconductor device equipped with the same Dec 18, 2011 Issued
Array ( [id] => 7818091 [patent_doc_number] => 20120064711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'COPPER BONDING COMPATIBLE BOND PAD STRUCTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/298455 [patent_app_country] => US [patent_app_date] => 2011-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1848 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20120064711.pdf [firstpage_image] =>[orig_patent_app_number] => 13298455 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/298455
Copper bonding compatible bond pad structure and method Nov 16, 2011 Issued
Array ( [id] => 7767216 [patent_doc_number] => 20120034741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'POWER DEVICE PACKAGE COMPRISING METAL TAB DIE ATTACH PADDLE (DAP) AND METHOD OF FABRICATING THE PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/278664 [patent_app_country] => US [patent_app_date] => 2011-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4281 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034741.pdf [firstpage_image] =>[orig_patent_app_number] => 13278664 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/278664
Power device package comprising metal tab die attach paddle (DAP) and method of fabricating the package Oct 20, 2011 Issued
Array ( [id] => 7767215 [patent_doc_number] => 20120034740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'PRE-ENCAPSULATED CAVITY INTERPOSER' [patent_app_type] => utility [patent_app_number] => 13/277988 [patent_app_country] => US [patent_app_date] => 2011-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7579 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20120034740.pdf [firstpage_image] =>[orig_patent_app_number] => 13277988 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/277988
Methods of forming and assembling pre-encapsulated assemblies and of forming associated semiconductor device packages Oct 19, 2011 Issued
Array ( [id] => 8689811 [patent_doc_number] => 08389338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Embedded die package on package (POP) with pre-molded leadframe' [patent_app_type] => utility [patent_app_number] => 13/276372 [patent_app_country] => US [patent_app_date] => 2011-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 43 [patent_no_of_words] => 2662 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13276372 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/276372
Embedded die package on package (POP) with pre-molded leadframe Oct 18, 2011 Issued
Array ( [id] => 7762801 [patent_doc_number] => 20120032325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-09 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/274738 [patent_app_country] => US [patent_app_date] => 2011-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7865 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20120032325.pdf [firstpage_image] =>[orig_patent_app_number] => 13274738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/274738
Semiconductor device Oct 16, 2011 Issued
Array ( [id] => 8127633 [patent_doc_number] => 20120088363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'METHOD AND SYSTEM FOR FORMING CONDUCTIVE BUMPING WITH COPPER INTERCONNECTION' [patent_app_type] => utility [patent_app_number] => 13/269538 [patent_app_country] => US [patent_app_date] => 2011-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5352 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20120088363.pdf [firstpage_image] =>[orig_patent_app_number] => 13269538 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/269538
Method and system for forming conductive bumping with copper interconnection Oct 6, 2011 Issued
Array ( [id] => 7750586 [patent_doc_number] => 20120025372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'CHIP HAVING A DRIVING INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/253076 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025372.pdf [firstpage_image] =>[orig_patent_app_number] => 13253076 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253076
Chip having a driving integrated circuit Oct 4, 2011 Issued
Array ( [id] => 8249165 [patent_doc_number] => 20120153489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING PROXIMITY COMMUNICATION SIGNAL INPUT TERMINALS AND MANUFACTURING METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 13/252850 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3303 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153489.pdf [firstpage_image] =>[orig_patent_app_number] => 13252850 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/252850
Semiconductor package having proximity communication signal input terminals and manufacturing methods thereof Oct 3, 2011 Issued
Array ( [id] => 8742690 [patent_doc_number] => 20130082407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'Integrated Circuit Package And Method' [patent_app_type] => utility [patent_app_number] => 13/252833 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252833 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/252833
Integrated Circuit Package And Method Oct 3, 2011 Abandoned
Array ( [id] => 8742668 [patent_doc_number] => 20130082385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-04 [patent_title] => 'DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER' [patent_app_type] => utility [patent_app_number] => 13/251498 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3461 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251498 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251498
Die having coefficient of thermal expansion graded layer Oct 2, 2011 Issued
Array ( [id] => 9167280 [patent_doc_number] => 08592963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Self-aligning structures and method for integrated chips' [patent_app_type] => utility [patent_app_number] => 13/251846 [patent_app_country] => US [patent_app_date] => 2011-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 20 [patent_no_of_words] => 3844 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13251846 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/251846
Self-aligning structures and method for integrated chips Oct 2, 2011 Issued
Menu