Search

Chris C. Chu

Examiner (ID: 8603)

Most Active Art Unit
2815
Art Unit(s)
2815
Total Applications
1003
Issued Applications
778
Pending Applications
1
Abandoned Applications
227

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9154220 [patent_doc_number] => 08587127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Semiconductor structures and methods of forming the same' [patent_app_type] => utility [patent_app_number] => 13/161153 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4651 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13161153 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161153
Semiconductor structures and methods of forming the same Jun 14, 2011 Issued
Array ( [id] => 8519892 [patent_doc_number] => 20120319300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH UNDERFILL AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/161368 [patent_app_country] => US [patent_app_date] => 2011-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13161368 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/161368
Integrated circuit packaging system with underfill and method of manufacture thereof Jun 14, 2011 Issued
Array ( [id] => 9232731 [patent_doc_number] => 08598035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-03 [patent_title] => 'Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same' [patent_app_type] => utility [patent_app_number] => 13/151495 [patent_app_country] => US [patent_app_date] => 2011-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 6019 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13151495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151495
Semiconductor dice with backside trenches filled with elastic material for improved attachment, packages using the same, and methods of making the same Jun 1, 2011 Issued
Array ( [id] => 8859147 [patent_doc_number] => 08461684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Cobalt nitride layers for copper interconnects and methods for forming them' [patent_app_type] => utility [patent_app_number] => 13/150992 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8562 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13150992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/150992
Cobalt nitride layers for copper interconnects and methods for forming them May 31, 2011 Issued
Array ( [id] => 8549188 [patent_doc_number] => 08324069 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-12-04 [patent_title] => 'Method of fabricating high-performance capacitors in integrated MOS technologies' [patent_app_type] => utility [patent_app_number] => 13/134159 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5342 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13134159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/134159
Method of fabricating high-performance capacitors in integrated MOS technologies May 30, 2011 Issued
Array ( [id] => 8969217 [patent_doc_number] => 08508033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/067154 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3840 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13067154 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/067154
Semiconductor device May 11, 2011 Issued
Array ( [id] => 8826020 [patent_doc_number] => 20130127065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-23 [patent_title] => 'CMUT DEVICES AND FABRICATION METHODS' [patent_app_type] => utility [patent_app_number] => 13/696294 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4946 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13696294 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/696294
CMUT devices and fabrication methods May 2, 2011 Issued
Array ( [id] => 6165978 [patent_doc_number] => 20110195565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-11 [patent_title] => 'Semiconductor Devices and Methods of Manufacture Thereof' [patent_app_type] => utility [patent_app_number] => 13/091612 [patent_app_country] => US [patent_app_date] => 2011-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7558 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20110195565.pdf [firstpage_image] =>[orig_patent_app_number] => 13091612 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/091612
Semiconductor devices and methods of manufacture thereof Apr 20, 2011 Issued
Array ( [id] => 7496860 [patent_doc_number] => 20110260300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Wafer-Bump Structure' [patent_app_type] => utility [patent_app_number] => 13/083745 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1331 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260300.pdf [firstpage_image] =>[orig_patent_app_number] => 13083745 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/083745
Wafer-bump structure Apr 10, 2011 Issued
Array ( [id] => 8858508 [patent_doc_number] => 08461043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Barrier layer for integrated circuit contacts' [patent_app_type] => utility [patent_app_number] => 13/083868 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1679 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13083868 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/083868
Barrier layer for integrated circuit contacts Apr 10, 2011 Issued
Array ( [id] => 5955748 [patent_doc_number] => 20110180822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'Optoelectronic Component' [patent_app_type] => utility [patent_app_number] => 13/084149 [patent_app_country] => US [patent_app_date] => 2011-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3813 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20110180822.pdf [firstpage_image] =>[orig_patent_app_number] => 13084149 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/084149
Optoelectronic component Apr 10, 2011 Issued
Array ( [id] => 7496865 [patent_doc_number] => 20110260305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'Power Semiconductor Device Packaging' [patent_app_type] => utility [patent_app_number] => 13/083531 [patent_app_country] => US [patent_app_date] => 2011-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 8073 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260305.pdf [firstpage_image] =>[orig_patent_app_number] => 13083531 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/083531
Power semiconductor device packaging Apr 8, 2011 Issued
Array ( [id] => 8591851 [patent_doc_number] => 08349727 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-08 [patent_title] => 'Integrated method for high-density interconnection of electronic components through stretchable interconnects' [patent_app_type] => utility [patent_app_number] => 13/083111 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3978 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13083111 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/083111
Integrated method for high-density interconnection of electronic components through stretchable interconnects Apr 7, 2011 Issued
Array ( [id] => 8642539 [patent_doc_number] => 08367522 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-02-05 [patent_title] => 'Method and structure of integrated micro electro-mechanical systems and electronic devices using edge bond pads' [patent_app_type] => utility [patent_app_number] => 13/082384 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5317 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13082384 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082384
Method and structure of integrated micro electro-mechanical systems and electronic devices using edge bond pads Apr 6, 2011 Issued
Array ( [id] => 8571643 [patent_doc_number] => 08338288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 13/081160 [patent_app_country] => US [patent_app_date] => 2011-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 44 [patent_no_of_words] => 20814 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13081160 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/081160
Method of manufacturing semiconductor device Apr 5, 2011 Issued
Array ( [id] => 8630442 [patent_doc_number] => 08362515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-29 [patent_title] => 'Chip package and method for forming the same' [patent_app_type] => utility [patent_app_number] => 13/081346 [patent_app_country] => US [patent_app_date] => 2011-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 6155 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13081346 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/081346
Chip package and method for forming the same Apr 5, 2011 Issued
Array ( [id] => 8439707 [patent_doc_number] => 20120256323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'METHOD FOR PROCESSING A SEMICONDUCTOR WAFER OR DIE, AND PARTICLE DEPOSITION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/080813 [patent_app_country] => US [patent_app_date] => 2011-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12281 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080813 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080813
Method for processing a semiconductor wafer or die, and particle deposition device Apr 5, 2011 Issued
Array ( [id] => 8533304 [patent_doc_number] => 08309458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Semiconductor device comprising variable-sized contact, method of forming same, and apparatus comprising same' [patent_app_type] => utility [patent_app_number] => 13/079941 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5035 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13079941 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/079941
Semiconductor device comprising variable-sized contact, method of forming same, and apparatus comprising same Apr 4, 2011 Issued
Array ( [id] => 8469734 [patent_doc_number] => 08298911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Methods of forming wiring structures' [patent_app_type] => utility [patent_app_number] => 13/080001 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 35 [patent_no_of_words] => 15329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080001 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080001
Methods of forming wiring structures Apr 4, 2011 Issued
Array ( [id] => 8439690 [patent_doc_number] => 20120256306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'EXPOSED DIE PACKAGE FOR DIRECT SURFACE MOUNTING' [patent_app_type] => utility [patent_app_number] => 13/080320 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2625 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13080320 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080320
Exposed die package for direct surface mounting Apr 4, 2011 Issued
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