Search

Christian A. Laforgia

Examiner (ID: 18559)

Most Active Art Unit
2439
Art Unit(s)
2139, 2439, 2155, 2131
Total Applications
477
Issued Applications
335
Pending Applications
23
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20624752 [patent_doc_number] => 12592264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-31 [patent_title] => Reduction in chip area through design-technology co-optimization [patent_app_type] => utility [patent_app_number] => 18/758643 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 31 [patent_no_of_words] => 15633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758643 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758643
Reduction in chip area through design-technology co-optimization Jun 27, 2024 Issued
Array ( [id] => 19696109 [patent_doc_number] => 20250014654 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/758496 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10117 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758496 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/758496
ADAPTIVE TEMPERATURE COMPENSATION FOR A MEMORY DEVICE Jun 27, 2024 Pending
Array ( [id] => 19993733 [patent_doc_number] => 20250131955 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => APPARATUSES AND METHODS FOR ROW HAMMER COUNTER INITIALIZATION [patent_app_type] => utility [patent_app_number] => 18/756919 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756919 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756919
APPARATUSES AND METHODS FOR ROW HAMMER COUNTER INITIALIZATION Jun 26, 2024 Pending
Array ( [id] => 19788257 [patent_doc_number] => 20250061936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS [patent_app_type] => utility [patent_app_number] => 18/754884 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754884 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754884
MICROELECTRONIC DEVICES AND MEMORY DEVICES INCLUDING VERTICALLY SPACED TRANSISTORS AND STORAGE DEVICES, AND RELATED ELECTRONIC SYSTEMS Jun 25, 2024 Pending
Array ( [id] => 20140040 [patent_doc_number] => 20250247084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-31 [patent_title] => MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/754433 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754433 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754433
MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF Jun 25, 2024 Pending
Array ( [id] => 19515433 [patent_doc_number] => 20240347119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/753717 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16429 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18753717 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/753717
MANAGING PROGRAM VERIFY VOLTAGE OFFSETS FOR CHARGE COUPLING AND LATERAL MIGRATION COMPENSATION IN MEMORY DEVICES Jun 24, 2024 Pending
Array ( [id] => 20214954 [patent_doc_number] => 12411606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => High capacity memory circuit with low effective latency [patent_app_type] => utility [patent_app_number] => 18/750979 [patent_app_country] => US [patent_app_date] => 2024-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 9805 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18750979 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/750979
High capacity memory circuit with low effective latency Jun 20, 2024 Issued
Array ( [id] => 19694713 [patent_doc_number] => 20250013258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING [patent_app_type] => utility [patent_app_number] => 18/749057 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749057
SYSTEMS AND TECHNIQUES FOR CLOCK DOUBLING Jun 19, 2024 Pending
Array ( [id] => 19500143 [patent_doc_number] => 20240339161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => NON-VOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/749001 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6182 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749001 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749001
NON-VOLATILE MEMORY DEVICE Jun 19, 2024 Pending
Array ( [id] => 19500142 [patent_doc_number] => 20240339160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => SEMICONDUCTOR MEMORY AND NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/746964 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 51231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746964 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746964
SEMICONDUCTOR MEMORY AND NONVOLATILE MEMORY Jun 17, 2024 Pending
Array ( [id] => 19486798 [patent_doc_number] => 20240334840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/742115 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18742115 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/742115
MAGNETIC TUNNELING JUNCTION DEVICE AND MEMORY DEVICE INCLUDING THE SAME Jun 12, 2024 Pending
Array ( [id] => 19483730 [patent_doc_number] => 20240331772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => CURRENT AND VOLTAGE LIMIT CIRCUITRY FOR RESISTIVE RANDOM ACCESS MEMORY PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/740981 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740981 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740981
Current and voltage limit circuitry for resistive random access memory programming Jun 11, 2024 Issued
Array ( [id] => 20101769 [patent_doc_number] => 20250231705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => COARSE AND FINE PROGRAMMING OF NON-VOLATILE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/648219 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648219 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648219
Coarse and fine programming of non-volatile memory cells Apr 25, 2024 Issued
Array ( [id] => 20323029 [patent_doc_number] => 20250335117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => WRITE DATA PATH FOR HIGH-SPEED TIME-SHARED SERIAL READ WRITE MEMORIES HAVING WRITE MASK [patent_app_type] => utility [patent_app_number] => 18/648222 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18648222 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/648222
WRITE DATA PATH FOR HIGH-SPEED TIME-SHARED SERIAL READ WRITE MEMORIES HAVING WRITE MASK Apr 25, 2024 Pending
Array ( [id] => 20109267 [patent_doc_number] => 12359978 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-15 [patent_title] => Temperature exception tracking in a temperature log for a memory system [patent_app_type] => utility [patent_app_number] => 18/646587 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 13710 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646587 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646587
Temperature exception tracking in a temperature log for a memory system Apr 24, 2024 Issued
Array ( [id] => 19544909 [patent_doc_number] => 20240361945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => INVERSE ERASE FOR MEMORY COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/645713 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645713 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645713
INVERSE ERASE FOR MEMORY COMPONENTS Apr 24, 2024 Pending
Array ( [id] => 19559634 [patent_doc_number] => 20240371426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Bank-Shared Usage-Based Disturbance Circuitry [patent_app_type] => utility [patent_app_number] => 18/635631 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8080 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635631 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635631
Bank-shared usage-based disturbance circuitry Apr 14, 2024 Issued
Array ( [id] => 20297619 [patent_doc_number] => 20250322862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-16 [patent_title] => AP-pinned Data Storage Layer and Laminated Topological Heusler Alloy SOT-MRAM Unit Cell for In-Memory Computing Artificial Intelligence Inference Chip [patent_app_type] => utility [patent_app_number] => 18/633153 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633153 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633153
AP-pinned Data Storage Layer and Laminated Topological Heusler Alloy SOT-MRAM Unit Cell for In-Memory Computing Artificial Intelligence Inference Chip Apr 10, 2024 Pending
Array ( [id] => 19335343 [patent_doc_number] => 20240249773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => NON-VOLATILE MEMORY AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/625956 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625956 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625956
Non-volatile memory and operating method thereof Apr 2, 2024 Issued
Array ( [id] => 20281559 [patent_doc_number] => 20250306801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => SELECT GATE BIAS GRADATION STRUCTURE IN NAND MEMORY [patent_app_type] => utility [patent_app_number] => 18/624399 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18624399 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/624399
Select gate bias gradation structure in NAND memory Apr 1, 2024 Issued
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