Search

Christian A. Laforgia

Examiner (ID: 18559)

Most Active Art Unit
2439
Art Unit(s)
2139, 2439, 2155, 2131
Total Applications
477
Issued Applications
335
Pending Applications
23
Abandoned Applications
119

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20080626 [patent_doc_number] => 12354701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Sense amplifier circuit and method [patent_app_type] => utility [patent_app_number] => 18/615497 [patent_app_country] => US [patent_app_date] => 2024-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1068 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18615497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/615497
Sense amplifier circuit and method Mar 24, 2024 Issued
Array ( [id] => 19481798 [patent_doc_number] => 20240329840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => MEMORY ARRAY CONFIGURATION FOR SHARED WORD LINES [patent_app_type] => utility [patent_app_number] => 18/607026 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607026
MEMORY ARRAY CONFIGURATION FOR SHARED WORD LINES Mar 14, 2024 Pending
Array ( [id] => 20649491 [patent_doc_number] => 12604454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-14 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/601832 [patent_app_country] => US [patent_app_date] => 2024-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 14924 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601832 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/601832
Memory device Mar 10, 2024 Issued
Array ( [id] => 20080570 [patent_doc_number] => 12354645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Memory with artificial intelligence mode [patent_app_type] => utility [patent_app_number] => 18/594666 [patent_app_country] => US [patent_app_date] => 2024-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10801 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18594666 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/594666
Memory with artificial intelligence mode Mar 3, 2024 Issued
Array ( [id] => 19321216 [patent_doc_number] => 20240242762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => Bit Line Pre-Charge Circuit for Power Management Modes in Multi Bank SRAM [patent_app_type] => utility [patent_app_number] => 18/585184 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18585184 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/585184
Bit line pre-charge circuit for power management modes in multi bank SRAM Feb 22, 2024 Issued
Array ( [id] => 19237090 [patent_doc_number] => 20240194285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-13 [patent_title] => MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/583294 [patent_app_country] => US [patent_app_date] => 2024-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583294 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583294
MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME Feb 20, 2024 Issued
Array ( [id] => 20181057 [patent_doc_number] => 20250265015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => FPGA MEMORY WITH AUTO ADDRESS MODE [patent_app_type] => utility [patent_app_number] => 18/581131 [patent_app_country] => US [patent_app_date] => 2024-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18581131 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/581131
FPGA MEMORY WITH AUTO ADDRESS MODE Feb 18, 2024 Pending
Array ( [id] => 19405413 [patent_doc_number] => 20240288924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/443955 [patent_app_country] => US [patent_app_date] => 2024-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11647 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18443955 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/443955
POWER ARBITRATION FOR SYSTEMS OF ELECTRONIC COMPONENTS Feb 15, 2024 Pending
Array ( [id] => 19986778 [patent_doc_number] => 20250125000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => SEMICONDUCTOR SYSTEM RELATED TO PERFORMING AN ERROR CHECK SCRUB OPERATION [patent_app_type] => utility [patent_app_number] => 18/441264 [patent_app_country] => US [patent_app_date] => 2024-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13245 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18441264 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/441264
Semiconductor system related to performing an error check scrub operation Feb 13, 2024 Issued
Array ( [id] => 19205855 [patent_doc_number] => 20240177754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-30 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/436025 [patent_app_country] => US [patent_app_date] => 2024-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -33 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18436025 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/436025
Memory system and operating method of the memory system Feb 7, 2024 Issued
Array ( [id] => 19435757 [patent_doc_number] => 20240304255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT THRESHOLDS BASED ON BIT SIGNIFICANCE [patent_app_type] => utility [patent_app_number] => 18/423181 [patent_app_country] => US [patent_app_date] => 2024-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44609 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18423181 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/423181
MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT THRESHOLDS BASED ON BIT SIGNIFICANCE Jan 24, 2024 Pending
Array ( [id] => 20611573 [patent_doc_number] => 12587182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Duty cycle correction circuit and duty cycle correcting method [patent_app_type] => utility [patent_app_number] => 18/404710 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404710 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404710
Duty cycle correction circuit and duty cycle correcting method Jan 3, 2024 Issued
Array ( [id] => 20088573 [patent_doc_number] => 20250218509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEGMENTED REFERENCE FOR TRACKING COLUMN LOADING [patent_app_type] => utility [patent_app_number] => 18/400921 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18400921 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/400921
SEGMENTED REFERENCE FOR TRACKING COLUMN LOADING Dec 28, 2023 Pending
Array ( [id] => 19320105 [patent_doc_number] => 20240241649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-18 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/399867 [patent_app_country] => US [patent_app_date] => 2023-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399867 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399867
Nonvolatile memory device and method of programming a nonvolatile memory Dec 28, 2023 Issued
Array ( [id] => 19285346 [patent_doc_number] => 20240221823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers And Methods For Operating Same [patent_app_type] => utility [patent_app_number] => 18/399579 [patent_app_country] => US [patent_app_date] => 2023-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18399579 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/399579
Dynamic Random Access Memory System Including Single-Ended Sense Amplifiers And Methods For Operating Same Dec 27, 2023 Pending
Array ( [id] => 20071864 [patent_doc_number] => 20250210086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) [patent_app_type] => utility [patent_app_number] => 18/394849 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2445 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394849 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394849
MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) Dec 21, 2023 Pending
Array ( [id] => 20071862 [patent_doc_number] => 20250210084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => APPARATUS AND METHODS FOR MANAGING SELECTOR DEVICE THRESHOLD VOLTAGE DRIFT [patent_app_type] => utility [patent_app_number] => 18/389987 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18389987 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/389987
APPARATUS AND METHODS FOR MANAGING SELECTOR DEVICE THRESHOLD VOLTAGE DRIFT Dec 19, 2023 Pending
Array ( [id] => 19084872 [patent_doc_number] => 20240111673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => MEMORY DEVICE INTERFACE AND METHOD [patent_app_type] => utility [patent_app_number] => 18/537357 [patent_app_country] => US [patent_app_date] => 2023-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18537357 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/537357
Memory device interface and method Dec 11, 2023 Issued
Array ( [id] => 19073329 [patent_doc_number] => 20240107755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => NON-VOLATILE MEMORY (NVM) CELL STRUCTURE TO INCREASE RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/534818 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14330 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18534818 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/534818
Non-volatile memory (NVM) cell structure to increase reliability Dec 10, 2023 Issued
Array ( [id] => 19100760 [patent_doc_number] => 20240119988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => DELAY CONTROL CIRCUIT, DELAY CONTROL METHOD AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/533165 [patent_app_country] => US [patent_app_date] => 2023-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10251 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18533165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/533165
Delay control circuit, delay control method and memory Dec 6, 2023 Issued
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