
Christian D. Wilson
Examiner (ID: 14512)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824, 2891, 2829 |
| Total Applications | 392 |
| Issued Applications | 358 |
| Pending Applications | 5 |
| Abandoned Applications | 29 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7287226
[patent_doc_number] => 20040147062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-29
[patent_title] => 'Filling plugs through chemical mechanical polish'
[patent_app_type] => new
[patent_app_number] => 10/757228
[patent_app_country] => US
[patent_app_date] => 2004-01-14
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4933
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[pdf_file] => publications/A1/0147/20040147062.pdf
[firstpage_image] =>[orig_patent_app_number] => 10757228
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/757228 | Filling plugs through chemical mechanical polish | Jan 13, 2004 | Issued |
Array
(
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[patent_doc_number] => 20040140052
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-22
[patent_title] => 'Method for aligning key in semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/747768
[patent_app_country] => US
[patent_app_date] => 2003-12-29
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/747768 | Method for aligning key in semiconductor device | Dec 28, 2003 | Abandoned |
Array
(
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[patent_doc_number] => 06977207
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[patent_issue_date] => 2005-12-20
[patent_title] => 'Method for fabricating dual-gate semiconductor device'
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[patent_app_country] => US
[patent_app_date] => 2003-12-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/744428 | Method for fabricating dual-gate semiconductor device | Dec 21, 2003 | Issued |
Array
(
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[patent_issue_date] => 2006-05-16
[patent_title] => 'Method for integrating high-k dielectrics in transistor devices'
[patent_app_type] => utility
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[patent_app_date] => 2003-12-17
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/738958 | Method for integrating high-k dielectrics in transistor devices | Dec 16, 2003 | Issued |
Array
(
[id] => 7324257
[patent_doc_number] => 20040137726
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[patent_issue_date] => 2004-07-15
[patent_title] => 'Underlayer film-forming material for copper, method for a forming underlayer film for copper, an underlayer film for copper, and a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/732798
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Array
(
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[patent_title] => 'Methods of forming semiconductor devices having field oxides in trenches and devices formed thereby'
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Array
(
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[patent_title] => 'Method for forming floating gate in flash memory device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/720408 | Method for forming floating gate in flash memory device | Nov 23, 2003 | Issued |
Array
(
[id] => 7304873
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[patent_issue_date] => 2004-06-17
[patent_title] => 'Production method for manufacturing a plurality of chip-size packages'
[patent_app_type] => new
[patent_app_number] => 10/718848
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[patent_app_date] => 2003-11-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/718848 | Production method for manufacturing a plurality of chip-size packages | Nov 20, 2003 | Issued |
Array
(
[id] => 7287872
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[patent_issue_date] => 2004-06-10
[patent_title] => 'Non-volatile memory and fabrication method thereof'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/716621 | Non-volatile memory and fabrication method thereof | Nov 19, 2003 | Issued |
Array
(
[id] => 790546
[patent_doc_number] => 06984566
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[patent_title] => 'Damascene gate process'
[patent_app_type] => utility
[patent_app_number] => 10/715658
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Array
(
[id] => 6918312
[patent_doc_number] => 20050095873
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[patent_issue_date] => 2005-05-05
[patent_title] => 'Method for the heat treatment of substrates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/700298 | Method for the heat treatment of substrates | Oct 30, 2003 | Issued |
Array
(
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Array
(
[id] => 991067
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[patent_title] => 'Magneto resistive storage device having a magnetic field sink layer'
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Array
(
[id] => 7189513
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Array
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Array
(
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Array
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Array
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