
Christian D. Wilson
Examiner (ID: 1080)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2829, 2891, 2824 |
| Total Applications | 392 |
| Issued Applications | 358 |
| Pending Applications | 5 |
| Abandoned Applications | 29 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7400626
[patent_doc_number] => 20040023464
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-05
[patent_title] => 'Method for fabricating a deep trench capacitor for dynamic memory cells'
[patent_app_type] => new
[patent_app_number] => 10/465488
[patent_app_country] => US
[patent_app_date] => 2003-06-19
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[pdf_file] => publications/A1/0023/20040023464.pdf
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Array
(
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[patent_doc_number] => 06852577
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[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Method for forming a low temperature polysilicon CMOS thin film transistor'
[patent_app_type] => utility
[patent_app_number] => 10/463348
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[patent_app_date] => 2003-06-18
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Array
(
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[patent_doc_number] => 20040259352
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[patent_kind] => A1
[patent_issue_date] => 2004-12-23
[patent_title] => 'Corrosion resistance for copper interconnects'
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[patent_app_number] => 10/463948
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/463948 | Corrosion resistance for copper interconnects | Jun 16, 2003 | Issued |
Array
(
[id] => 1256155
[patent_doc_number] => 06667236
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[patent_kind] => B2
[patent_issue_date] => 2003-12-23
[patent_title] => 'Method of manufacturing a two layer liner for dual damascene vias'
[patent_app_type] => B2
[patent_app_number] => 10/462845
[patent_app_country] => US
[patent_app_date] => 2003-06-16
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/462845 | Method of manufacturing a two layer liner for dual damascene vias | Jun 15, 2003 | Issued |
Array
(
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[patent_issue_date] => 2006-01-17
[patent_title] => 'Methods to planarize semiconductor device and passivation layer'
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[patent_app_number] => 10/460878
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Array
(
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[patent_issue_date] => 2005-06-21
[patent_title] => 'Method of manufacturing a FeRAM with annealing process'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/457588 | Method for manufacturing semiconductor device | Jun 9, 2003 | Abandoned |
Array
(
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[patent_title] => 'Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask'
[patent_app_type] => utility
[patent_app_number] => 10/454518
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Array
(
[id] => 1156156
[patent_doc_number] => 06762098
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-07-13
[patent_title] => 'Trench DMOS transistor with embedded trench schottky rectifier'
[patent_app_type] => B2
[patent_app_number] => 10/448791
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/448791 | Trench DMOS transistor with embedded trench schottky rectifier | May 29, 2003 | Issued |
Array
(
[id] => 7264025
[patent_doc_number] => 20040241913
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[patent_issue_date] => 2004-12-02
[patent_title] => 'High impedance radio frequency power plastic package'
[patent_app_type] => new
[patent_app_number] => 10/448548
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/448548 | High impedance radio frequency power plastic package | May 29, 2003 | Issued |
Array
(
[id] => 1017882
[patent_doc_number] => 06890776
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[patent_issue_date] => 2005-05-10
[patent_title] => 'Silicon oxide film evaluation method and semiconductor device fabrication method'
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Array
(
[id] => 982315
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/445188 | Manufacturing a bump electrode with roughened face | May 26, 2003 | Issued |
Array
(
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Array
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Array
(
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Array
(
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Array
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Array
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