Search

Christian D. Wilson

Examiner (ID: 1080)

Most Active Art Unit
2824
Art Unit(s)
2829, 2891, 2824
Total Applications
392
Issued Applications
358
Pending Applications
5
Abandoned Applications
29

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7400626 [patent_doc_number] => 20040023464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Method for fabricating a deep trench capacitor for dynamic memory cells' [patent_app_type] => new [patent_app_number] => 10/465488 [patent_app_country] => US [patent_app_date] => 2003-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2961 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023464.pdf [firstpage_image] =>[orig_patent_app_number] => 10465488 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/465488
Method for fabricating a deep trench capacitor for dynamic memory cells Jun 18, 2003 Issued
Array ( [id] => 1059487 [patent_doc_number] => 06852577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method for forming a low temperature polysilicon CMOS thin film transistor' [patent_app_type] => utility [patent_app_number] => 10/463348 [patent_app_country] => US [patent_app_date] => 2003-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 3608 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852577.pdf [firstpage_image] =>[orig_patent_app_number] => 10463348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463348
Method for forming a low temperature polysilicon CMOS thin film transistor Jun 17, 2003 Issued
Array ( [id] => 7253178 [patent_doc_number] => 20040259352 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Corrosion resistance for copper interconnects' [patent_app_type] => new [patent_app_number] => 10/463948 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1993 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20040259352.pdf [firstpage_image] =>[orig_patent_app_number] => 10463948 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463948
Corrosion resistance for copper interconnects Jun 16, 2003 Issued
Array ( [id] => 1256155 [patent_doc_number] => 06667236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-23 [patent_title] => 'Method of manufacturing a two layer liner for dual damascene vias' [patent_app_type] => B2 [patent_app_number] => 10/462845 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1718 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/667/06667236.pdf [firstpage_image] =>[orig_patent_app_number] => 10462845 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462845
Method of manufacturing a two layer liner for dual damascene vias Jun 15, 2003 Issued
Array ( [id] => 788136 [patent_doc_number] => 06987068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Methods to planarize semiconductor device and passivation layer' [patent_app_type] => utility [patent_app_number] => 10/460878 [patent_app_country] => US [patent_app_date] => 2003-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 5592 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987068.pdf [firstpage_image] =>[orig_patent_app_number] => 10460878 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460878
Methods to planarize semiconductor device and passivation layer Jun 13, 2003 Issued
Array ( [id] => 1002413 [patent_doc_number] => 06908867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'Method of manufacturing a FeRAM with annealing process' [patent_app_type] => utility [patent_app_number] => 10/460248 [patent_app_country] => US [patent_app_date] => 2003-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 25 [patent_no_of_words] => 6556 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/908/06908867.pdf [firstpage_image] =>[orig_patent_app_number] => 10460248 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/460248
Method of manufacturing a FeRAM with annealing process Jun 12, 2003 Issued
Array ( [id] => 7467014 [patent_doc_number] => 20040102048 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/457588 [patent_app_country] => US [patent_app_date] => 2003-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9030 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20040102048.pdf [firstpage_image] =>[orig_patent_app_number] => 10457588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/457588
Method for manufacturing semiconductor device Jun 9, 2003 Abandoned
Array ( [id] => 1046793 [patent_doc_number] => 06864188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-08 [patent_title] => 'Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask' [patent_app_type] => utility [patent_app_number] => 10/454518 [patent_app_country] => US [patent_app_date] => 2003-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2506 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864188.pdf [firstpage_image] =>[orig_patent_app_number] => 10454518 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454518
Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask Jun 3, 2003 Issued
Array ( [id] => 1156156 [patent_doc_number] => 06762098 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-13 [patent_title] => 'Trench DMOS transistor with embedded trench schottky rectifier' [patent_app_type] => B2 [patent_app_number] => 10/448791 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 4365 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/762/06762098.pdf [firstpage_image] =>[orig_patent_app_number] => 10448791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448791
Trench DMOS transistor with embedded trench schottky rectifier May 29, 2003 Issued
Array ( [id] => 7264025 [patent_doc_number] => 20040241913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-02 [patent_title] => 'High impedance radio frequency power plastic package' [patent_app_type] => new [patent_app_number] => 10/448548 [patent_app_country] => US [patent_app_date] => 2003-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3056 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0241/20040241913.pdf [firstpage_image] =>[orig_patent_app_number] => 10448548 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/448548
High impedance radio frequency power plastic package May 29, 2003 Issued
Array ( [id] => 1017882 [patent_doc_number] => 06890776 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Silicon oxide film evaluation method and semiconductor device fabrication method' [patent_app_type] => utility [patent_app_number] => 10/446928 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3298 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890776.pdf [firstpage_image] =>[orig_patent_app_number] => 10446928 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446928
Silicon oxide film evaluation method and semiconductor device fabrication method May 28, 2003 Issued
Array ( [id] => 982315 [patent_doc_number] => 06927159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Methods for providing improved layer adhesion in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/446898 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4314 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927159.pdf [firstpage_image] =>[orig_patent_app_number] => 10446898 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446898
Methods for providing improved layer adhesion in a semiconductor device May 26, 2003 Issued
Array ( [id] => 7357161 [patent_doc_number] => 20040004273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Semiconductor device and method for making the same' [patent_app_type] => new [patent_app_number] => 10/445188 [patent_app_country] => US [patent_app_date] => 2003-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2929 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004273.pdf [firstpage_image] =>[orig_patent_app_number] => 10445188 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445188
Manufacturing a bump electrode with roughened face May 26, 2003 Issued
Array ( [id] => 7619732 [patent_doc_number] => 06943454 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Memory module' [patent_app_type] => utility [patent_app_number] => 10/445283 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4805 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/943/06943454.pdf [firstpage_image] =>[orig_patent_app_number] => 10445283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445283
Memory module May 22, 2003 Issued
Array ( [id] => 724323 [patent_doc_number] => 07045396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Stackable semiconductor package and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/439671 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4663 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045396.pdf [firstpage_image] =>[orig_patent_app_number] => 10439671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439671
Stackable semiconductor package and method for manufacturing same May 15, 2003 Issued
Array ( [id] => 988148 [patent_doc_number] => 06921703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'System and method for mitigating oxide growth in a gate dielectric' [patent_app_type] => utility [patent_app_number] => 10/436848 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6272 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/921/06921703.pdf [firstpage_image] =>[orig_patent_app_number] => 10436848 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436848
System and method for mitigating oxide growth in a gate dielectric May 12, 2003 Issued
Array ( [id] => 1101765 [patent_doc_number] => 06815346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Unique feature design enabling structural integrity for advanced low k semiconductor chips' [patent_app_type] => B2 [patent_app_number] => 10/437208 [patent_app_country] => US [patent_app_date] => 2003-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3606 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815346.pdf [firstpage_image] =>[orig_patent_app_number] => 10437208 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437208
Unique feature design enabling structural integrity for advanced low k semiconductor chips May 12, 2003 Issued
Array ( [id] => 1014601 [patent_doc_number] => 06893943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Method of dividing a semiconductor wafer' [patent_app_type] => utility [patent_app_number] => 10/431816 [patent_app_country] => US [patent_app_date] => 2003-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 3307 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893943.pdf [firstpage_image] =>[orig_patent_app_number] => 10431816 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431816
Method of dividing a semiconductor wafer May 7, 2003 Issued
Array ( [id] => 7429530 [patent_doc_number] => 20040209486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-21 [patent_title] => 'STI formation for vertical and planar transistors' [patent_app_type] => new [patent_app_number] => 10/419588 [patent_app_country] => US [patent_app_date] => 2003-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9448 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0209/20040209486.pdf [firstpage_image] =>[orig_patent_app_number] => 10419588 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/419588
STI formation for vertical and planar transistors Apr 20, 2003 Issued
Array ( [id] => 751825 [patent_doc_number] => 07023048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-04 [patent_title] => 'Nonvolatile semiconductor memory devices and the fabrication process of them' [patent_app_type] => utility [patent_app_number] => 10/417269 [patent_app_country] => US [patent_app_date] => 2003-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 141 [patent_no_of_words] => 17242 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/023/07023048.pdf [firstpage_image] =>[orig_patent_app_number] => 10417269 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/417269
Nonvolatile semiconductor memory devices and the fabrication process of them Apr 16, 2003 Issued
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