
Christian D. Wilson
Examiner (ID: 10232)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824, 2829, 2891 |
| Total Applications | 392 |
| Issued Applications | 358 |
| Pending Applications | 5 |
| Abandoned Applications | 29 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1059488
[patent_doc_number] => 06852578
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL'
[patent_app_type] => utility
[patent_app_number] => 10/346502
[patent_app_country] => US
[patent_app_date] => 2003-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 29
[patent_no_of_words] => 8830
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/852/06852578.pdf
[firstpage_image] =>[orig_patent_app_number] => 10346502
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/346502 | Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL | Jan 14, 2003 | Issued |
Array
(
[id] => 1254291
[patent_doc_number] => 06670681
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[patent_kind] => B2
[patent_issue_date] => 2003-12-30
[patent_title] => 'Semiconductor structures'
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[patent_app_country] => US
[patent_app_date] => 2003-01-13
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[firstpage_image] =>[orig_patent_app_number] => 10341925
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Array
(
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[patent_doc_number] => 20030180988
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[patent_issue_date] => 2003-09-25
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/339678
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[patent_app_date] => 2003-01-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/339678 | Semiconductor device having multiple semiconductor chips in a single package | Jan 9, 2003 | Issued |
Array
(
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[patent_doc_number] => 20040130947
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[patent_issue_date] => 2004-07-08
[patent_title] => 'Flash memory with trench select gate and fabrication process'
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[patent_app_number] => 10/336639
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[patent_app_date] => 2003-01-02
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Array
(
[id] => 996562
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[patent_issue_date] => 2005-07-05
[patent_title] => 'Differential planarization'
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Array
(
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[patent_issue_date] => 2003-07-10
[patent_title] => 'Methods for making multiple seed layers for metallic interconnects'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/328629 | Methods for making multiple seed layers for metallic interconnects | Dec 22, 2002 | Issued |
Array
(
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[patent_doc_number] => 20030124775
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[patent_title] => 'Semiconductor device, semiconductor device manufacturing method, circuit board, and electronic device'
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[patent_app_date] => 2002-12-20
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[pdf_file] => publications/A1/0124/20030124775.pdf
[firstpage_image] =>[orig_patent_app_number] => 10324938
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/324938 | Semiconductor device with protrusions | Dec 19, 2002 | Issued |
Array
(
[id] => 7471242
[patent_doc_number] => 20040121501
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[patent_kind] => A1
[patent_issue_date] => 2004-06-24
[patent_title] => 'Low dielectric constant interconnect insulator having fullerene additive'
[patent_app_type] => new
[patent_app_number] => 10/322868
[patent_app_country] => US
[patent_app_date] => 2002-12-18
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[pdf_file] => publications/A1/0121/20040121501.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/322868 | Low dielectric constant interconnect insulator having fullerene additive | Dec 17, 2002 | Abandoned |
Array
(
[id] => 1146463
[patent_doc_number] => 06774006
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[patent_issue_date] => 2004-08-10
[patent_title] => 'Microelectronic device fabricating method, and method of forming a pair of field effect transistor gate lines of different base widths from a common deposited conductive layer'
[patent_app_type] => B2
[patent_app_number] => 10/323525
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/323525 | Microelectronic device fabricating method, and method of forming a pair of field effect transistor gate lines of different base widths from a common deposited conductive layer | Dec 17, 2002 | Issued |
Array
(
[id] => 6865261
[patent_doc_number] => 20030190787
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[patent_issue_date] => 2003-10-09
[patent_title] => 'Process for realizing a channel scaled and small body gradient VDMOS for high current densities and low driving voltages'
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[patent_app_number] => 10/319438
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Array
(
[id] => 1155866
[patent_doc_number] => 06764941
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[patent_issue_date] => 2004-07-20
[patent_title] => 'Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof'
[patent_app_type] => B2
[patent_app_number] => 10/316709
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/316709 | Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof | Dec 10, 2002 | Issued |
Array
(
[id] => 1005343
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[patent_title] => 'Method of forming interconnect structure with low dielectric constant'
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Array
(
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[patent_title] => 'Method of dual damascene patterning'
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Array
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[patent_title] => 'Method of forming a protective step on the edge of a semiconductor wafer'
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Array
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Array
(
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[patent_title] => 'Irradiation of manufacturing a thin film transistor by laser irradiation'
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/273306 | Metal gate stack with etch stop layer | Oct 17, 2002 | Issued |