Search

Christian D. Wilson

Examiner (ID: 10232)

Most Active Art Unit
2824
Art Unit(s)
2824, 2829, 2891
Total Applications
392
Issued Applications
358
Pending Applications
5
Abandoned Applications
29

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1059488 [patent_doc_number] => 06852578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL' [patent_app_type] => utility [patent_app_number] => 10/346502 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 8830 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852578.pdf [firstpage_image] =>[orig_patent_app_number] => 10346502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/346502
Schottky diode static random access memory (DSRAM) device, a method for making same, and CFET based DTL Jan 14, 2003 Issued
Array ( [id] => 1254291 [patent_doc_number] => 06670681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Semiconductor structures' [patent_app_type] => B2 [patent_app_number] => 10/341925 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4996 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670681.pdf [firstpage_image] =>[orig_patent_app_number] => 10341925 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/341925
Semiconductor structures Jan 12, 2003 Issued
Array ( [id] => 6829930 [patent_doc_number] => 20030180988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/339678 [patent_app_country] => US [patent_app_date] => 2003-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6187 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20030180988.pdf [firstpage_image] =>[orig_patent_app_number] => 10339678 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/339678
Semiconductor device having multiple semiconductor chips in a single package Jan 9, 2003 Issued
Array ( [id] => 7331144 [patent_doc_number] => 20040130947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-08 [patent_title] => 'Flash memory with trench select gate and fabrication process' [patent_app_type] => new [patent_app_number] => 10/336639 [patent_app_country] => US [patent_app_date] => 2003-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6415 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20040130947.pdf [firstpage_image] =>[orig_patent_app_number] => 10336639 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/336639
Flash memory with trench select gate and fabrication process Jan 1, 2003 Issued
Array ( [id] => 996562 [patent_doc_number] => 06914002 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Differential planarization' [patent_app_type] => utility [patent_app_number] => 10/334308 [patent_app_country] => US [patent_app_date] => 2002-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3178 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914002.pdf [firstpage_image] =>[orig_patent_app_number] => 10334308 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/334308
Differential planarization Dec 27, 2002 Issued
Array ( [id] => 6856327 [patent_doc_number] => 20030129828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'Methods for making multiple seed layers for metallic interconnects' [patent_app_type] => new [patent_app_number] => 10/328629 [patent_app_country] => US [patent_app_date] => 2002-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9923 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20030129828.pdf [firstpage_image] =>[orig_patent_app_number] => 10328629 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/328629
Methods for making multiple seed layers for metallic interconnects Dec 22, 2002 Issued
Array ( [id] => 6761413 [patent_doc_number] => 20030124775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Semiconductor device, semiconductor device manufacturing method, circuit board, and electronic device' [patent_app_type] => new [patent_app_number] => 10/324938 [patent_app_country] => US [patent_app_date] => 2002-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4370 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124775.pdf [firstpage_image] =>[orig_patent_app_number] => 10324938 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/324938
Semiconductor device with protrusions Dec 19, 2002 Issued
Array ( [id] => 7471242 [patent_doc_number] => 20040121501 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Low dielectric constant interconnect insulator having fullerene additive' [patent_app_type] => new [patent_app_number] => 10/322868 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1067 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 12 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121501.pdf [firstpage_image] =>[orig_patent_app_number] => 10322868 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/322868
Low dielectric constant interconnect insulator having fullerene additive Dec 17, 2002 Abandoned
Array ( [id] => 1146463 [patent_doc_number] => 06774006 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-10 [patent_title] => 'Microelectronic device fabricating method, and method of forming a pair of field effect transistor gate lines of different base widths from a common deposited conductive layer' [patent_app_type] => B2 [patent_app_number] => 10/323525 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3811 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/774/06774006.pdf [firstpage_image] =>[orig_patent_app_number] => 10323525 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/323525
Microelectronic device fabricating method, and method of forming a pair of field effect transistor gate lines of different base widths from a common deposited conductive layer Dec 17, 2002 Issued
Array ( [id] => 6865261 [patent_doc_number] => 20030190787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Process for realizing a channel scaled and small body gradient VDMOS for high current densities and low driving voltages' [patent_app_type] => new [patent_app_number] => 10/319438 [patent_app_country] => US [patent_app_date] => 2002-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2765 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20030190787.pdf [firstpage_image] =>[orig_patent_app_number] => 10319438 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/319438
Process for realizing a channel scaled and small body gradient VDMOS for high current densities and low driving voltages Dec 12, 2002 Abandoned
Array ( [id] => 1155866 [patent_doc_number] => 06764941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof' [patent_app_type] => B2 [patent_app_number] => 10/316709 [patent_app_country] => US [patent_app_date] => 2002-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4562 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/764/06764941.pdf [firstpage_image] =>[orig_patent_app_number] => 10316709 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/316709
Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof Dec 10, 2002 Issued
Array ( [id] => 1005343 [patent_doc_number] => 06905938 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Method of forming interconnect structure with low dielectric constant' [patent_app_type] => utility [patent_app_number] => 10/315128 [patent_app_country] => US [patent_app_date] => 2002-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1847 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905938.pdf [firstpage_image] =>[orig_patent_app_number] => 10315128 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/315128
Method of forming interconnect structure with low dielectric constant Dec 9, 2002 Issued
Array ( [id] => 1202727 [patent_doc_number] => 06720256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-13 [patent_title] => 'Method of dual damascene patterning' [patent_app_type] => B1 [patent_app_number] => 10/309428 [patent_app_country] => US [patent_app_date] => 2002-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6959 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/720/06720256.pdf [firstpage_image] =>[orig_patent_app_number] => 10309428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/309428
Method of dual damascene patterning Dec 3, 2002 Issued
Array ( [id] => 1119867 [patent_doc_number] => 06797625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method of forming a protective step on the edge of a semiconductor wafer' [patent_app_type] => B2 [patent_app_number] => 10/306238 [patent_app_country] => US [patent_app_date] => 2002-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2366 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797625.pdf [firstpage_image] =>[orig_patent_app_number] => 10306238 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/306238
Method of forming a protective step on the edge of a semiconductor wafer Nov 26, 2002 Issued
Array ( [id] => 1119709 [patent_doc_number] => 06797568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-28 [patent_title] => 'Flash technology transistors and methods for forming the same' [patent_app_type] => B1 [patent_app_number] => 10/302439 [patent_app_country] => US [patent_app_date] => 2002-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 39 [patent_no_of_words] => 4127 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797568.pdf [firstpage_image] =>[orig_patent_app_number] => 10302439 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/302439
Flash technology transistors and methods for forming the same Nov 20, 2002 Issued
Array ( [id] => 1205477 [patent_doc_number] => 06716688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Irradiation of manufacturing a thin film transistor by laser irradiation' [patent_app_type] => B2 [patent_app_number] => 10/299218 [patent_app_country] => US [patent_app_date] => 2002-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 6190 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716688.pdf [firstpage_image] =>[orig_patent_app_number] => 10299218 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/299218
Irradiation of manufacturing a thin film transistor by laser irradiation Nov 17, 2002 Issued
Array ( [id] => 7612459 [patent_doc_number] => 06903377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Light emitting apparatus and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/290478 [patent_app_country] => US [patent_app_date] => 2002-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 53 [patent_no_of_words] => 15665 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/903/06903377.pdf [firstpage_image] =>[orig_patent_app_number] => 10290478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/290478
Light emitting apparatus and method for manufacturing the same Nov 7, 2002 Issued
Array ( [id] => 6674388 [patent_doc_number] => 20030059991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Laser processing method' [patent_app_type] => new [patent_app_number] => 10/288365 [patent_app_country] => US [patent_app_date] => 2002-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 21941 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20030059991.pdf [firstpage_image] =>[orig_patent_app_number] => 10288365 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/288365
Laser processing method Nov 5, 2002 Issued
Array ( [id] => 6720946 [patent_doc_number] => 20030054635 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Fabrication of a metalized blind via' [patent_app_type] => new [patent_app_number] => 10/282275 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3928 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20030054635.pdf [firstpage_image] =>[orig_patent_app_number] => 10282275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/282275
Fabrication of a metalized blind via Oct 27, 2002 Issued
Array ( [id] => 7632730 [patent_doc_number] => 06664604 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Metal gate stack with etch stop layer' [patent_app_type] => B1 [patent_app_number] => 10/273306 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3169 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/664/06664604.pdf [firstpage_image] =>[orig_patent_app_number] => 10273306 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273306
Metal gate stack with etch stop layer Oct 17, 2002 Issued
Menu