Search

Christina A. Sylvia

Examiner (ID: 14390, Phone: (571)272-7474 , Office: P/2895 )

Most Active Art Unit
2895
Art Unit(s)
2895, 2817
Total Applications
885
Issued Applications
727
Pending Applications
84
Abandoned Applications
97

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18097462 [patent_doc_number] => 20220415803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-29 [patent_title] => WAFER-LEVEL ASIC 3D INTEGRATED SUBSTRATE, PACKAGING DEVICE AND PREPARATION METHOD [patent_app_type] => utility [patent_app_number] => 17/851870 [patent_app_country] => US [patent_app_date] => 2022-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17851870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/851870
Wafer-level ASIC 3D integrated substrate, packaging device and preparation method Jun 27, 2022 Issued
Array ( [id] => 20869881 [patent_doc_number] => 12696800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-28 [patent_title] => Microelectronic assemblies including solder and non-solder interconnects [patent_app_type] => utility [patent_app_number] => 17/848246 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 20 [patent_no_of_words] => 10917 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848246 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848246
MICROELECTRONIC ASSEMBLIES INCLUDING SOLDER AND NON-SOLDER INTERCONNECTS Jun 22, 2022 Pending
Array ( [id] => 17917626 [patent_doc_number] => 20220320022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/846596 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10040 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846596 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846596
Manufacturing method of semiconductor structure Jun 21, 2022 Issued
Array ( [id] => 18112940 [patent_doc_number] => 20230005820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => FULLY MOLDED SEMICONDUCTOR STRUCTURE WITH THROUGH SILICON VIA (TSV) VERTICAL INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 17/842491 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842491 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842491
Fully molded semiconductor structure with through silicon via (TSV) vertical interconnects Jun 15, 2022 Issued
Array ( [id] => 18633591 [patent_doc_number] => 20230292518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/842411 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7976 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842411
Three-dimensional type NAND memory device Jun 15, 2022 Issued
Array ( [id] => 19654495 [patent_doc_number] => 12176295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Semiconductor device package and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/840435 [patent_app_country] => US [patent_app_date] => 2022-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5610 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17840435 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/840435
Semiconductor device package and method of manufacturing the same Jun 13, 2022 Issued
Array ( [id] => 20404452 [patent_doc_number] => 12494433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => 3D embedded redistribution layers for IC substrate packaging [patent_app_type] => utility [patent_app_number] => 17/806660 [patent_app_country] => US [patent_app_date] => 2022-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4681 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17806660 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/806660
3D embedded redistribution layers for IC substrate packaging Jun 12, 2022 Issued
Array ( [id] => 19765975 [patent_doc_number] => 12224276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => 3D semiconductor packages [patent_app_type] => utility [patent_app_number] => 17/837039 [patent_app_country] => US [patent_app_date] => 2022-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 43 [patent_no_of_words] => 9965 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17837039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/837039
3D semiconductor packages Jun 9, 2022 Issued
Array ( [id] => 19928267 [patent_doc_number] => 12302578 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-13 [patent_title] => Non-volatile memory device [patent_app_type] => utility [patent_app_number] => 17/834977 [patent_app_country] => US [patent_app_date] => 2022-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 12702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17834977 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/834977
Non-volatile memory device Jun 7, 2022 Issued
Array ( [id] => 18631769 [patent_doc_number] => 20230290674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => Dielectric Layers Having Nitrogen-Containing Crusted Surfaces [patent_app_type] => utility [patent_app_number] => 17/833395 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17833395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/833395
Dielectric layers having nitrogen-containing crusted surfaces Jun 5, 2022 Issued
Array ( [id] => 20470973 [patent_doc_number] => 12527019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Method of manufacturing semiconductor devices having metal gate structure and semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/832306 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 5957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832306
Method of manufacturing semiconductor devices having metal gate structure and semiconductor devices Jun 2, 2022 Issued
Array ( [id] => 18812633 [patent_doc_number] => 20230386970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => NANO THROUGH SUBSTRATE VIAS FOR SEMICONDUCTOR DEVICES AND RELATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/827006 [patent_app_country] => US [patent_app_date] => 2022-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6608 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17827006 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/827006
Nano through substrate vias for semiconductor devices and related systems and methods May 26, 2022 Issued
Array ( [id] => 18812997 [patent_doc_number] => 20230387334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => METHOD FOR MANUFACTURING INTEGRATED CIRCUIT DEVICE AND INTEGRATED CIRCUIT DEVICE THEREOF [patent_app_type] => utility [patent_app_number] => 17/824923 [patent_app_country] => US [patent_app_date] => 2022-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6561 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17824923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/824923
Method for manufacturing silicon photonic device and silicon photonic device thereof May 25, 2022 Issued
Array ( [id] => 17855411 [patent_doc_number] => 20220285454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/664801 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9292 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664801 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664801
Display panel, manufacturing method thereof and display device May 23, 2022 Issued
Array ( [id] => 17855412 [patent_doc_number] => 20220285455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/664809 [patent_app_country] => US [patent_app_date] => 2022-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9567 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17664809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/664809
Display panel, manufacturing method thereof and display device May 23, 2022 Issued
Array ( [id] => 20734844 [patent_doc_number] => 12642112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Wiring substrate and electronic device [patent_app_type] => utility [patent_app_number] => 18/026083 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18026083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/026083
Wiring substrate and electronic device May 19, 2022 Issued
Array ( [id] => 18224996 [patent_doc_number] => 20230063990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SEMICONDUCTOR APPARATUS, SOCKET, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 17/747311 [patent_app_country] => US [patent_app_date] => 2022-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19305 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17747311 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/747311
SEMICONDUCTOR APPARATUS, SOCKET, AND ELECTRONIC APPARATUS May 17, 2022 Abandoned
Array ( [id] => 18935547 [patent_doc_number] => 11887991 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => Display apparatus and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/745427 [patent_app_country] => US [patent_app_date] => 2022-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 10900 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17745427 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/745427
Display apparatus and method of manufacturing the same May 15, 2022 Issued
Array ( [id] => 19341469 [patent_doc_number] => 12051666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-30 [patent_title] => Package structure and manufacturing method of package structure thereof [patent_app_type] => utility [patent_app_number] => 17/739200 [patent_app_country] => US [patent_app_date] => 2022-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 7216 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17739200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/739200
Package structure and manufacturing method of package structure thereof May 8, 2022 Issued
Array ( [id] => 19063182 [patent_doc_number] => 11942434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Method of manufacturing a semiconductor package [patent_app_type] => utility [patent_app_number] => 17/731841 [patent_app_country] => US [patent_app_date] => 2022-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7356 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17731841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/731841
Method of manufacturing a semiconductor package Apr 27, 2022 Issued
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