Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19604664 [patent_doc_number] => 20240395544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => DEPOSITION AND TREATMENT OF NANO-GRAPHENE AT LOW TEMPERATURES [patent_app_type] => utility [patent_app_number] => 18/694600 [patent_app_country] => US [patent_app_date] => 2022-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18694600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/694600
DEPOSITION AND TREATMENT OF NANO-GRAPHENE AT LOW TEMPERATURES Sep 28, 2022 Pending
Array ( [id] => 19071345 [patent_doc_number] => 20240105771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => INTEGRATED CIRCUIT STRUCTURES WITH CHANNEL CAP REDUCTION [patent_app_type] => utility [patent_app_number] => 17/955485 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17288 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17955485 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/955485
INTEGRATED CIRCUIT STRUCTURES WITH CHANNEL CAP REDUCTION Sep 27, 2022 Pending
Array ( [id] => 18145200 [patent_doc_number] => 20230019055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/954844 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9676 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954844 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954844
Semiconductor device Sep 27, 2022 Issued
Array ( [id] => 19634621 [patent_doc_number] => 20240413070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => VIAS INCLUDING A POROUS ELECTRICALLY CONDUCTIVE MATERIAL AND METHODS FOR FABRICATING THE VIAS [patent_app_type] => utility [patent_app_number] => 18/700432 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5691 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18700432 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/700432
VIAS INCLUDING A POROUS ELECTRICALLY CONDUCTIVE MATERIAL AND METHODS FOR FABRICATING THE VIAS Sep 27, 2022 Pending
Array ( [id] => 19071378 [patent_doc_number] => 20240105804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS [patent_app_type] => utility [patent_app_number] => 17/954194 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17405 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954194
INTEGRATED CIRCUIT STRUCTURES HAVING FIN ISOLATION REGIONS BOUND BY GATE CUTS Sep 26, 2022 Pending
Array ( [id] => 19071290 [patent_doc_number] => 20240105716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TRENCH CONTACT PLUG [patent_app_type] => utility [patent_app_number] => 17/954206 [patent_app_country] => US [patent_app_date] => 2022-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18990 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17954206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/954206
INTEGRATED CIRCUIT STRUCTURES HAVING UNIFORM GRID METAL GATE AND TRENCH CONTACT PLUG Sep 26, 2022 Pending
Array ( [id] => 19071374 [patent_doc_number] => 20240105800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => MULTI-STAGE MASK ETCH PROCESS [patent_app_type] => utility [patent_app_number] => 17/951532 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15810 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17951532 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/951532
MULTI-STAGE MASK ETCH PROCESS Sep 22, 2022 Pending
Array ( [id] => 19071185 [patent_doc_number] => 20240105611 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => BACKSIDE SIGNAL INTEGRATION THROUGH VIA TO SIGNAL LINE CONNECTION [patent_app_type] => utility [patent_app_number] => 17/950293 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6599 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950293 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950293
BACKSIDE SIGNAL INTEGRATION THROUGH VIA TO SIGNAL LINE CONNECTION Sep 21, 2022 Pending
Array ( [id] => 19071371 [patent_doc_number] => 20240105797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => TRANSISTOR DEVICES WITH DOUBLE-SIDE CONTACTS [patent_app_type] => utility [patent_app_number] => 17/934400 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934400
Transistor devices with double-side contacts Sep 21, 2022 Issued
Array ( [id] => 20443150 [patent_doc_number] => 12513996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Three-dimensional semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 17/950434 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 8017 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17950434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/950434
Three-dimensional semiconductor device and method of fabricating the same Sep 21, 2022 Issued
Array ( [id] => 19054922 [patent_doc_number] => 20240096891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SELF-ALIGNED BACKSIDE CONTACT [patent_app_type] => utility [patent_app_number] => 17/946821 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4870 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946821
SELF-ALIGNED BACKSIDE CONTACT Sep 15, 2022 Pending
Array ( [id] => 19054982 [patent_doc_number] => 20240096951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => STACKED FETS WITH CONTACT PLACEHOLDER STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/946546 [patent_app_country] => US [patent_app_date] => 2022-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17946546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/946546
Stacked FETS with contact placeholder structures Sep 15, 2022 Issued
Array ( [id] => 18344298 [patent_doc_number] => 20230132408 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => Method for Manufacturing Metal Gate of PMOS [patent_app_type] => utility [patent_app_number] => 17/945356 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 435 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17945356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/945356
Method for manufacturing metal gate of PMOS Sep 14, 2022 Issued
Array ( [id] => 19038403 [patent_doc_number] => 20240088218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => GATE CUTS IN A GRATING PATTERN ACROSS AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/943443 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17943443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/943443
GATE CUTS IN A GRATING PATTERN ACROSS AN INTEGRATED CIRCUIT Sep 12, 2022 Pending
Array ( [id] => 19007984 [patent_doc_number] => 20240072055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/897151 [patent_app_country] => US [patent_app_date] => 2022-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13558 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897151 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897151
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME Aug 26, 2022 Pending
Array ( [id] => 18712918 [patent_doc_number] => 20230335551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE [patent_app_type] => utility [patent_app_number] => 17/896970 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10463 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17896970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/896970
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE Aug 25, 2022 Pending
Array ( [id] => 18424161 [patent_doc_number] => 20230178625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-08 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/892415 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13713 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892415
Semiconductor device Aug 21, 2022 Issued
Array ( [id] => 18866129 [patent_doc_number] => 20230420566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => SEMICONDUCTOR DEVICE WITH REVERSE-CUT SOURCE/DRAIN CONTACT STRUCTURE AND METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/892864 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892864 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892864
Semiconductor device with reverse-cut source/drain contact structure and method thereof Aug 21, 2022 Issued
Array ( [id] => 18991220 [patent_doc_number] => 20240063189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => STACKED LONG CHANNEL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/820264 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5800 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820264 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820264
STACKED LONG CHANNEL TRANSISTOR Aug 16, 2022 Pending
Array ( [id] => 18361952 [patent_doc_number] => 20230143543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/819936 [patent_app_country] => US [patent_app_date] => 2022-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819936
Semiconductor device and method of manufacturing the semiconductor device Aug 14, 2022 Issued
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