Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19094022 [patent_doc_number] => 11955487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/886878 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 10096 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17886878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/886878
Semiconductor device Aug 11, 2022 Issued
Array ( [id] => 18040050 [patent_doc_number] => 20220384267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/884518 [patent_app_country] => US [patent_app_date] => 2022-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17884518 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/884518
Semiconductor device and forming method thereof Aug 8, 2022 Issued
Array ( [id] => 18024315 [patent_doc_number] => 20220375814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => Thermal Interface Materials, 3D Semiconductor Packages and Methods of Manufacture [patent_app_type] => utility [patent_app_number] => 17/883348 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17883348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/883348
Thermal interface materials, 3D semiconductor packages and methods of manufacture Aug 7, 2022 Issued
Array ( [id] => 19328830 [patent_doc_number] => 12046519 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Metal gates and methods of forming thereby [patent_app_type] => utility [patent_app_number] => 17/882165 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 10270 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882165 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882165
Metal gates and methods of forming thereby Aug 4, 2022 Issued
Array ( [id] => 19183776 [patent_doc_number] => 11990376 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Selective dual silicide formation [patent_app_type] => utility [patent_app_number] => 17/816039 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 8132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816039
Selective dual silicide formation Jul 28, 2022 Issued
Array ( [id] => 19356992 [patent_doc_number] => 12057449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Isolation structures for semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/816044 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 52 [patent_no_of_words] => 7267 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816044 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816044
Isolation structures for semiconductor devices Jul 28, 2022 Issued
Array ( [id] => 18008904 [patent_doc_number] => 20220367671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-17 [patent_title] => GATE STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/815682 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9841 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815682 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815682
Gate structure of semiconductor device and method of forming same Jul 27, 2022 Issued
Array ( [id] => 19294536 [patent_doc_number] => 12033900 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-09 [patent_title] => Trench isolation with conductive structures [patent_app_type] => utility [patent_app_number] => 17/815094 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 9734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17815094 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/815094
Trench isolation with conductive structures Jul 25, 2022 Issued
Array ( [id] => 17993676 [patent_doc_number] => 20220359713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Fin Field-Effect Transistor and Method of Forming The Same [patent_app_type] => utility [patent_app_number] => 17/873853 [patent_app_country] => US [patent_app_date] => 2022-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11697 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17873853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/873853
Fin field-effect transistor and method of forming the same Jul 25, 2022 Issued
Array ( [id] => 17993472 [patent_doc_number] => 20220359509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => NOVEL LINER STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/872348 [patent_app_country] => US [patent_app_date] => 2022-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17872348 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/872348
Liner structures Jul 24, 2022 Issued
Array ( [id] => 19016422 [patent_doc_number] => 11923367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Low resistance fill metal layer material as stressor in metal gates [patent_app_type] => utility [patent_app_number] => 17/870964 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 12110 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17870964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/870964
Low resistance fill metal layer material as stressor in metal gates Jul 21, 2022 Issued
Array ( [id] => 17993658 [patent_doc_number] => 20220359695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE WITH METAL GATE STACK [patent_app_type] => utility [patent_app_number] => 17/871528 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10152 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871528
Semiconductor device structure with metal gate stack Jul 21, 2022 Issued
Array ( [id] => 18927306 [patent_doc_number] => 20240030310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/871645 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/871645
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME Jul 21, 2022 Issued
Array ( [id] => 18950971 [patent_doc_number] => 11894277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Transistor gates and methods of forming thereof [patent_app_type] => utility [patent_app_number] => 17/869590 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 77 [patent_no_of_words] => 13293 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869590
Transistor gates and methods of forming thereof Jul 19, 2022 Issued
Array ( [id] => 17986124 [patent_doc_number] => 20220352161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => BOUNDARY DESIGN FOR HIGH-VOLTAGE INTEGRATION ON HKMG TECHNOLOGY [patent_app_type] => utility [patent_app_number] => 17/867771 [patent_app_country] => US [patent_app_date] => 2022-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7270 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17867771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/867771
Boundary design for high-voltage integration on HKMG technology Jul 18, 2022 Issued
Array ( [id] => 19229784 [patent_doc_number] => 12009428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Semiconductor device and method [patent_app_type] => utility [patent_app_number] => 17/812874 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 11295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/812874
Semiconductor device and method Jul 14, 2022 Issued
Array ( [id] => 17985997 [patent_doc_number] => 20220352034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/865040 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7328 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17865040 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/865040
Semiconductor device and method of fabricating the same Jul 13, 2022 Issued
Array ( [id] => 18906223 [patent_doc_number] => 20240021708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/864894 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9745 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864894 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864894
STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH POWER RAIL Jul 13, 2022 Pending
Array ( [id] => 20509044 [patent_doc_number] => 12543336 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Methods of manufacturing semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/863741 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 2220 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17863741 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/863741
Methods of manufacturing semiconductor devices Jul 12, 2022 Issued
Array ( [id] => 17963629 [patent_doc_number] => 20220344210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-27 [patent_title] => GATE STRUCTURE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/811651 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17811651 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/811651
Gate structure and method of forming same Jul 10, 2022 Issued
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