Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18631783 [patent_doc_number] => 20230290688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD [patent_app_type] => utility [patent_app_number] => 17/654408 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654408 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/654408
Semiconductor device and method Mar 10, 2022 Issued
Array ( [id] => 19168527 [patent_doc_number] => 11984441 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-14 [patent_title] => Integrated circuit with backside power rail and backside interconnect [patent_app_type] => utility [patent_app_number] => 17/693153 [patent_app_country] => US [patent_app_date] => 2022-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 13269 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17693153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/693153
Integrated circuit with backside power rail and backside interconnect Mar 10, 2022 Issued
Array ( [id] => 18473169 [patent_doc_number] => 20230207457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => METHOD AND STRUCTURE FOR METAL TRACKS IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/690595 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690595 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690595
Method and structure for metal tracks in semiconductor devices Mar 8, 2022 Issued
Array ( [id] => 18578885 [patent_doc_number] => 11735425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Fin field-effect transistor and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/688364 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688364 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688364
Fin field-effect transistor and method of forming the same Mar 6, 2022 Issued
Array ( [id] => 17676972 [patent_doc_number] => 20220190139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => METHOD FOR FORMING SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/688236 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688236 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/688236
Method for forming semiconductor structure Mar 6, 2022 Issued
Array ( [id] => 17765056 [patent_doc_number] => 20220238669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => SEMICONDUCTOR DEVICE, FINFET DEVICE AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/685401 [patent_app_country] => US [patent_app_date] => 2022-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17685401 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/685401
Semiconductor device, FinFET device and methods of forming the same Mar 2, 2022 Issued
Array ( [id] => 17840944 [patent_doc_number] => 20220278250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => SEMICONDUCTOR LIGHT EMITTING ELEMENT AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING ELEMENT [patent_app_type] => utility [patent_app_number] => 17/680158 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680158 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680158
Semiconductor light emitting element and method of manufacturing semiconductor light emitting element Feb 23, 2022 Issued
Array ( [id] => 18373353 [patent_doc_number] => 11653545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-16 [patent_title] => Transparent display device [patent_app_type] => utility [patent_app_number] => 17/679974 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11687 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17679974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/679974
Transparent display device Feb 23, 2022 Issued
Array ( [id] => 20405578 [patent_doc_number] => 12495568 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-09 [patent_title] => Dummy Fin structures and methods of forming same [patent_app_type] => utility [patent_app_number] => 17/676470 [patent_app_country] => US [patent_app_date] => 2022-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 44 [patent_no_of_words] => 9139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17676470 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/676470
Dummy Fin structures and methods of forming same Feb 20, 2022 Issued
Array ( [id] => 17840911 [patent_doc_number] => 20220278217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => HIGH DIELECTRIC CONSTANT METAL GATE MOS TRANSISTOR AND METHOD FOR MAKING THE SAME [patent_app_type] => utility [patent_app_number] => 17/675809 [patent_app_country] => US [patent_app_date] => 2022-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17675809 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/675809
HIGH DIELECTRIC CONSTANT METAL GATE MOS TRANSISTOR AND METHOD FOR MAKING THE SAME Feb 17, 2022 Abandoned
Array ( [id] => 20259069 [patent_doc_number] => 12431434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-30 [patent_title] => Built-in component board, method of manufacturing the built-in component board [patent_app_type] => utility [patent_app_number] => 17/674231 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 30 [patent_no_of_words] => 6115 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674231
Built-in component board, method of manufacturing the built-in component board Feb 16, 2022 Issued
Array ( [id] => 17645486 [patent_doc_number] => 20220173225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => Dummy Gate Cutting Process and Resulting Gate Structures [patent_app_type] => utility [patent_app_number] => 17/650942 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8338 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17650942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/650942
Dummy gate cutting process and resulting gate structures Feb 13, 2022 Issued
Array ( [id] => 17645391 [patent_doc_number] => 20220173130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => PANEL, ELECTRONIC DEVICE AND TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/671452 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671452
Panel, electronic device and transistor Feb 13, 2022 Issued
Array ( [id] => 17645391 [patent_doc_number] => 20220173130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => PANEL, ELECTRONIC DEVICE AND TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/671452 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671452
Panel, electronic device and transistor Feb 13, 2022 Issued
Array ( [id] => 18464354 [patent_doc_number] => 11688648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Gate structure of a semiconductor device and method of forming same [patent_app_type] => utility [patent_app_number] => 17/671145 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 20945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671145
Gate structure of a semiconductor device and method of forming same Feb 13, 2022 Issued
Array ( [id] => 17645391 [patent_doc_number] => 20220173130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => PANEL, ELECTRONIC DEVICE AND TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/671452 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671452
Panel, electronic device and transistor Feb 13, 2022 Issued
Array ( [id] => 17645391 [patent_doc_number] => 20220173130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => PANEL, ELECTRONIC DEVICE AND TRANSISTOR [patent_app_type] => utility [patent_app_number] => 17/671452 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9172 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17671452 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/671452
Panel, electronic device and transistor Feb 13, 2022 Issued
Array ( [id] => 18828916 [patent_doc_number] => 11844217 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-12 [patent_title] => Methods for forming multi-layer vertical nor-type memory string arrays [patent_app_type] => utility [patent_app_number] => 17/669024 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 5309 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669024 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/669024
Methods for forming multi-layer vertical nor-type memory string arrays Feb 9, 2022 Issued
Array ( [id] => 17615475 [patent_doc_number] => 20220157755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => Method and System for Packing Optimization of Semiconductor Devices [patent_app_type] => utility [patent_app_number] => 17/588525 [patent_app_country] => US [patent_app_date] => 2022-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17588525 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/588525
Method and system for packing optimization of semiconductor devices Jan 30, 2022 Issued
Array ( [id] => 17599581 [patent_doc_number] => 20220149155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => CORE-SHELL NANOSTRUCTURES FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/582866 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582866 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582866
Core-shell nanostructures for semiconductor devices Jan 23, 2022 Issued
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