
Christine A. Enad
Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )
| Most Active Art Unit | 2811 |
| Art Unit(s) | 2823, 2811, 4116 |
| Total Applications | 1524 |
| Issued Applications | 1218 |
| Pending Applications | 124 |
| Abandoned Applications | 210 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17692535
[patent_doc_number] => 20220199828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => FIN TRANSISTORS WITH DOPED CONTROL LAYER FOR JUNCTION CONTROL
[patent_app_type] => utility
[patent_app_number] => 17/128545
[patent_app_country] => US
[patent_app_date] => 2020-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9006
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17128545
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/128545 | FIN TRANSISTORS WITH DOPED CONTROL LAYER FOR JUNCTION CONTROL | Dec 20, 2020 | Pending |
Array
(
[id] => 18416170
[patent_doc_number] => 11670719
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-06
[patent_title] => Semiconductor device having upper channel and lower channel and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 17/126260
[patent_app_country] => US
[patent_app_date] => 2020-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 46
[patent_no_of_words] => 6923
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17126260
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/126260 | Semiconductor device having upper channel and lower channel and method of manufacturing the same | Dec 17, 2020 | Issued |
Array
(
[id] => 16827969
[patent_doc_number] => 20210143262
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-13
[patent_title] => CONTACT PHOTOLITHOGRAPHY-BASED NANOPATTERNING USING PHOTORESIST FEATURES HAVING RE-ENTRANT PROFILES
[patent_app_type] => utility
[patent_app_number] => 17/123453
[patent_app_country] => US
[patent_app_date] => 2020-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5470
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123453
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/123453 | Contact photolithography-based nanopatterning using photoresist features having re-entrant profiles | Dec 15, 2020 | Issued |
Array
(
[id] => 16812323
[patent_doc_number] => 20210134878
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-05-06
[patent_title] => System and Method for Making Micro LED Display
[patent_app_type] => utility
[patent_app_number] => 17/120757
[patent_app_country] => US
[patent_app_date] => 2020-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9685
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17120757
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/120757 | System and Method for Making Micro LED Display | Dec 13, 2020 | Abandoned |
Array
(
[id] => 17486095
[patent_doc_number] => 20220093599
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => METHOD FOR MANUFACTURING FIN FIELD-EFFECT TRANSISTOR AND FIN FIELD-EFFECT TRANSISTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/107002
[patent_app_country] => US
[patent_app_date] => 2020-11-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 359
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107002
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/107002 | Method for manufacturing fin field-effect transistor and fin field-effect transistor structure | Nov 29, 2020 | Issued |
Array
(
[id] => 16715842
[patent_doc_number] => 20210082989
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-18
[patent_title] => PHOTOELECTRIC CONVERSION ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/102123
[patent_app_country] => US
[patent_app_date] => 2020-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15609
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17102123
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/102123 | PHOTOELECTRIC CONVERSION ELEMENT, IMAGING DEVICE, AND ELECTRONIC APPARATUS | Nov 22, 2020 | Abandoned |
Array
(
[id] => 17716687
[patent_doc_number] => 11380686
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-05
[patent_title] => Semiconductor devices including work function layers
[patent_app_type] => utility
[patent_app_number] => 17/101472
[patent_app_country] => US
[patent_app_date] => 2020-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 43
[patent_no_of_words] => 10153
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17101472
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/101472 | Semiconductor devices including work function layers | Nov 22, 2020 | Issued |
Array
(
[id] => 16692208
[patent_doc_number] => 20210074687
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => HIGH DENSITY PIXELATED LED AND DEVICES AND METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/950142
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38117
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950142
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950142 | High density pixelated LED and devices and methods thereof | Nov 16, 2020 | Issued |
Array
(
[id] => 16692208
[patent_doc_number] => 20210074687
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => HIGH DENSITY PIXELATED LED AND DEVICES AND METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/950142
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38117
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950142
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950142 | High density pixelated LED and devices and methods thereof | Nov 16, 2020 | Issued |
Array
(
[id] => 16692208
[patent_doc_number] => 20210074687
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => HIGH DENSITY PIXELATED LED AND DEVICES AND METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/950142
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38117
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950142
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950142 | High density pixelated LED and devices and methods thereof | Nov 16, 2020 | Issued |
Array
(
[id] => 16692208
[patent_doc_number] => 20210074687
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => HIGH DENSITY PIXELATED LED AND DEVICES AND METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/950142
[patent_app_country] => US
[patent_app_date] => 2020-11-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 38117
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16950142
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/950142 | High density pixelated LED and devices and methods thereof | Nov 16, 2020 | Issued |
Array
(
[id] => 17745644
[patent_doc_number] => 11393726
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Metal gate structure of a CMOS semiconductor device and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/098927
[patent_app_country] => US
[patent_app_date] => 2020-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5027
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17098927
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/098927 | Metal gate structure of a CMOS semiconductor device and method of forming the same | Nov 15, 2020 | Issued |
Array
(
[id] => 18579129
[patent_doc_number] => 11735669
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-22
[patent_title] => Vertically-oriented complementary transistor
[patent_app_type] => utility
[patent_app_number] => 17/094904
[patent_app_country] => US
[patent_app_date] => 2020-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 12111
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094904
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094904 | Vertically-oriented complementary transistor | Nov 10, 2020 | Issued |
Array
(
[id] => 16677317
[patent_doc_number] => 20210066083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-04
[patent_title] => METHOD FOR DEPOSITING A RUTHENIUM-CONTAINING FILM ON A SUBSTRATE BY A CYCLICAL DEPOSITION PROCESS
[patent_app_type] => utility
[patent_app_number] => 17/094049
[patent_app_country] => US
[patent_app_date] => 2020-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9827
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094049
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/094049 | Method for depositing a ruthenium-containing film on a substrate by a cyclical deposition process | Nov 9, 2020 | Issued |
Array
(
[id] => 17318945
[patent_doc_number] => 20210407995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-30
[patent_title] => Method of Tuning Threshold Voltages of Transistors
[patent_app_type] => utility
[patent_app_number] => 17/089291
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8050
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089291
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089291 | Method of tuning threshold voltages of transistors | Nov 3, 2020 | Issued |
Array
(
[id] => 17566828
[patent_doc_number] => 20220130977
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/081875
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6902
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081875
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081875 | Semiconductor devices and methods of manufacturing thereof | Oct 26, 2020 | Issued |
Array
(
[id] => 17978591
[patent_doc_number] => 11495463
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-08
[patent_title] => Semiconductor device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/081879
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 22
[patent_no_of_words] => 8350
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081879
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081879 | Semiconductor device and manufacturing method thereof | Oct 26, 2020 | Issued |
Array
(
[id] => 17886752
[patent_doc_number] => 20220302230
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-22
[patent_title] => ARRAY SUBSTRATE AND DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/428945
[patent_app_country] => US
[patent_app_date] => 2020-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 31977
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17428945
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/428945 | Array substrate and display apparatus | Oct 18, 2020 | Issued |
Array
(
[id] => 18431781
[patent_doc_number] => 11677013
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-13
[patent_title] => Source/drain epitaxial layers for transistors
[patent_app_type] => utility
[patent_app_number] => 17/072418
[patent_app_country] => US
[patent_app_date] => 2020-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6707
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17072418
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/072418 | Source/drain epitaxial layers for transistors | Oct 15, 2020 | Issued |
Array
(
[id] => 17536910
[patent_doc_number] => 20220115519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => FIN FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/070634
[patent_app_country] => US
[patent_app_date] => 2020-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11671
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17070634
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/070634 | Fin field-effect transistor and method of forming the same | Oct 13, 2020 | Issued |