Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17536921 [patent_doc_number] => 20220115530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => Dielectric Fin Structure [patent_app_type] => utility [patent_app_number] => 17/069409 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069409 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069409
Dielectric fin structure Oct 12, 2020 Issued
Array ( [id] => 18190623 [patent_doc_number] => 11581224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Method for forming long channel back-side power rail device [patent_app_type] => utility [patent_app_number] => 17/068037 [patent_app_country] => US [patent_app_date] => 2020-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 66 [patent_no_of_words] => 11808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17068037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/068037
Method for forming long channel back-side power rail device Oct 11, 2020 Issued
Array ( [id] => 16578966 [patent_doc_number] => 20210013367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => System and Method for Making Micro LED Display [patent_app_type] => utility [patent_app_number] => 17/036504 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12751 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036504 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036504
System and Method for Making Micro LED Display Sep 28, 2020 Abandoned
Array ( [id] => 16578804 [patent_doc_number] => 20210013205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-14 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/035296 [patent_app_country] => US [patent_app_date] => 2020-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10332 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17035296 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/035296
Semiconductor device and manufacturing method thereof Sep 27, 2020 Issued
Array ( [id] => 17486092 [patent_doc_number] => 20220093596 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER [patent_app_type] => utility [patent_app_number] => 17/030346 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030346 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030346
FABRICATION OF GATE-ALL-AROUND INTEGRATED CIRCUIT STRUCTURES HAVING COMMON METAL GATES AND HAVING GATE DIELECTRICS WITH A DIPOLE LAYER Sep 22, 2020 Issued
Array ( [id] => 17410406 [patent_doc_number] => 11251306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Integrated circuit device [patent_app_type] => utility [patent_app_number] => 17/028191 [patent_app_country] => US [patent_app_date] => 2020-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 62 [patent_figures_cnt] => 62 [patent_no_of_words] => 13740 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17028191 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/028191
Integrated circuit device Sep 21, 2020 Issued
Array ( [id] => 17952231 [patent_doc_number] => 11478303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Method and apparatus for determining implant positions of two medical implant components forming a joint [patent_app_type] => utility [patent_app_number] => 17/027198 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 9017 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17027198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/027198
Method and apparatus for determining implant positions of two medical implant components forming a joint Sep 20, 2020 Issued
Array ( [id] => 17956504 [patent_doc_number] => 11482619 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-25 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 17/026551 [patent_app_country] => US [patent_app_date] => 2020-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 9175 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026551
Semiconductor devices Sep 20, 2020 Issued
Array ( [id] => 17373951 [patent_doc_number] => 20220029003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SOURCE AND DRAIN EPITAXY FORMING METHOD CAPABLE OF IMPROVING PERFORMANCE OF FINFET DEVICE [patent_app_type] => utility [patent_app_number] => 17/026075 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17026075 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/026075
Source and drain epitaxy forming method capable of improving performance of FinFET device Sep 17, 2020 Issued
Array ( [id] => 17485964 [patent_doc_number] => 20220093468 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/025970 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025970 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025970
Semiconductor device and forming method thereof Sep 17, 2020 Issued
Array ( [id] => 18494281 [patent_doc_number] => 11699702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Input/output devices [patent_app_type] => utility [patent_app_number] => 17/025802 [patent_app_country] => US [patent_app_date] => 2020-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 12922 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17025802 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/025802
Input/output devices Sep 17, 2020 Issued
Array ( [id] => 16560358 [patent_doc_number] => 20210005507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-07 [patent_title] => HIGH RESISTIVITY SOI WAFERS AND A METHOD OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 16/948376 [patent_app_country] => US [patent_app_date] => 2020-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10041 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16948376 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/948376
High resistivity SOI wafers and a method of manufacturing thereof Sep 15, 2020 Issued
Array ( [id] => 18797111 [patent_doc_number] => 11830948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 17/019366 [patent_app_country] => US [patent_app_date] => 2020-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7618 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17019366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/019366
Semiconductor device and manufacturing method thereof Sep 13, 2020 Issued
Array ( [id] => 17303022 [patent_doc_number] => 20210398861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => METAL GATES AND METHODS OF FORMING THEREBY [patent_app_type] => utility [patent_app_number] => 17/018084 [patent_app_country] => US [patent_app_date] => 2020-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10256 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17018084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/018084
Metal gates and methods of forming thereby Sep 10, 2020 Issued
Array ( [id] => 16586235 [patent_doc_number] => 20210020637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-21 [patent_title] => COMPACT FINFET CMOS [patent_app_type] => utility [patent_app_number] => 16/974016 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16974016 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/974016
Compact FINFET CMOS Sep 7, 2020 Issued
Array ( [id] => 16528997 [patent_doc_number] => 20200403078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => Gate Structure and Patterning Method for Multiple Threshold Voltages [patent_app_type] => utility [patent_app_number] => 17/012832 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17012832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/012832
Gate structure and patterning method for multiple threshold voltages Sep 3, 2020 Issued
Array ( [id] => 17318810 [patent_doc_number] => 20210407860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SOLID-PHASE SOURCE DOPING METHOD FOR FINFET STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/005152 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17005152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/005152
Solid-phase source doping method for FinFET structure Aug 26, 2020 Issued
Array ( [id] => 17018598 [patent_doc_number] => 11088245 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Integrated circuit device with source/drain barrier [patent_app_type] => utility [patent_app_number] => 17/001464 [patent_app_country] => US [patent_app_date] => 2020-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17001464 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/001464
Integrated circuit device with source/drain barrier Aug 23, 2020 Issued
Array ( [id] => 17431774 [patent_doc_number] => 20220059483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => CONDUCTIVE PILLAR BUMP AND MANUFACTURING METHOD THEREFORE [patent_app_type] => utility [patent_app_number] => 16/996826 [patent_app_country] => US [patent_app_date] => 2020-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16996826 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/996826
CONDUCTIVE PILLAR BUMP AND MANUFACTURING METHOD THEREFORE Aug 17, 2020 Abandoned
Array ( [id] => 17078020 [patent_doc_number] => 11114436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Metal gate structure and methods thereof [patent_app_type] => utility [patent_app_number] => 16/947758 [patent_app_country] => US [patent_app_date] => 2020-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16947758 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/947758
Metal gate structure and methods thereof Aug 13, 2020 Issued
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