Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16456195 [patent_doc_number] => 20200365621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS [patent_app_type] => utility [patent_app_number] => 16/983463 [patent_app_country] => US [patent_app_date] => 2020-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7531 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16983463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/983463
Systems and methods for a semiconductor structure having multiple semiconductor-device layers Aug 2, 2020 Issued
Array ( [id] => 17381159 [patent_doc_number] => 11239192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Method and system for packing optimization of semiconductor devices [patent_app_type] => utility [patent_app_number] => 16/943015 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 8760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943015
Method and system for packing optimization of semiconductor devices Jul 29, 2020 Issued
Array ( [id] => 17389639 [patent_doc_number] => 20220037491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-03 [patent_title] => STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH METAL GATE STACK [patent_app_type] => utility [patent_app_number] => 16/943672 [patent_app_country] => US [patent_app_date] => 2020-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10124 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16943672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/943672
Structure and formation method of semiconductor device with metal gate stack Jul 29, 2020 Issued
Array ( [id] => 17174092 [patent_doc_number] => 20210327763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => Dummy Fin with Reduced Height and Method Forming Same [patent_app_type] => utility [patent_app_number] => 16/942076 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942076 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942076
Dummy fin with reduced height and method forming same Jul 28, 2020 Issued
Array ( [id] => 17925988 [patent_doc_number] => 11469252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/942093 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 9659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942093 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942093
Semiconductor device Jul 28, 2020 Issued
Array ( [id] => 16440373 [patent_doc_number] => 20200357700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => METHOD OF FORMING MULTI-THRESHOLD VOLTAGE DEVICES USING DIPOLE-HIGH DIELECTRIC CONSTANT COMBINATIONS AND DEVICES SO FORMED [patent_app_type] => utility [patent_app_number] => 16/942762 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16942762 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/942762
Method of forming multi-threshold voltage devices using dipole-high dielectric constant combinations and devices so formed Jul 28, 2020 Issued
Array ( [id] => 17917439 [patent_doc_number] => 20220319835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => LAMINATION WAFERS AND METHOD OF PRODUCING BONDED WAFERS USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/623639 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17623639 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/623639
Lamination wafers and method of producing bonded wafers using the same Jul 26, 2020 Issued
Array ( [id] => 18983669 [patent_doc_number] => 11908858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 16/937912 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 33 [patent_no_of_words] => 20408 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937912
Semiconductor device Jul 23, 2020 Issued
Array ( [id] => 16601537 [patent_doc_number] => 20210028068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-01-28 [patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/938168 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6380 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938168 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/938168
Semiconductor devices and methods of forming the same Jul 23, 2020 Issued
Array ( [id] => 17900867 [patent_doc_number] => 20220310529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => HEAT DISSIPATION-ELECTROMAGNETIC SHIELDING EMBEDDED PACKAGING STRUCTURE, MANUFACTURING METHOD THEREOF, AND SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/428822 [patent_app_country] => US [patent_app_date] => 2020-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6426 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17428822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/428822
Heat dissipation-electromagnetic shielding embedded packaging structure, manufacturing method thereof, and substrate Jul 23, 2020 Issued
Array ( [id] => 16995486 [patent_doc_number] => 20210233906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/937297 [patent_app_country] => US [patent_app_date] => 2020-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7247 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16937297 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/937297
Isolation structures for semiconductor devices Jul 22, 2020 Issued
Array ( [id] => 17347191 [patent_doc_number] => 20220013522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => SEMICONDUCTOR DEVICE IMPLEMENTED WITH BURIED RAILS [patent_app_type] => utility [patent_app_number] => 16/924757 [patent_app_country] => US [patent_app_date] => 2020-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924757 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/924757
Semiconductor device implemented with buried rails Jul 8, 2020 Issued
Array ( [id] => 17818721 [patent_doc_number] => 11424346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor device with programmable feature and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/916654 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 8119 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916654
Semiconductor device with programmable feature and method for fabricating the same Jun 29, 2020 Issued
Array ( [id] => 17745646 [patent_doc_number] => 11393728 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Semiconductor device and method of fabricating the same [patent_app_type] => utility [patent_app_number] => 16/917317 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7310 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917317 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917317
Semiconductor device and method of fabricating the same Jun 29, 2020 Issued
Array ( [id] => 17410195 [patent_doc_number] => 11251092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Gate structure of a semiconductor device and method of forming same [patent_app_type] => utility [patent_app_number] => 16/914880 [patent_app_country] => US [patent_app_date] => 2020-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 19840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914880 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914880
Gate structure of a semiconductor device and method of forming same Jun 28, 2020 Issued
Array ( [id] => 16379276 [patent_doc_number] => 20200328119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/914287 [patent_app_country] => US [patent_app_date] => 2020-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/914287
Semiconductor device and manufacturing method thereof Jun 26, 2020 Issued
Array ( [id] => 16379305 [patent_doc_number] => 20200328148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-15 [patent_title] => Semiconductor Device and Layout Design Thereof [patent_app_type] => utility [patent_app_number] => 16/913697 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913697 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913697
Semiconductor device and layout design thereof Jun 25, 2020 Issued
Array ( [id] => 17825746 [patent_doc_number] => 11430700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Trench isolation with conductive structures [patent_app_type] => utility [patent_app_number] => 16/913429 [patent_app_country] => US [patent_app_date] => 2020-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 9671 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/913429
Trench isolation with conductive structures Jun 25, 2020 Issued
Array ( [id] => 19328962 [patent_doc_number] => 12046654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => Integrated circuit structures including a titanium silicide material [patent_app_type] => utility [patent_app_number] => 16/912118 [patent_app_country] => US [patent_app_date] => 2020-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 22 [patent_no_of_words] => 11431 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16912118 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/912118
Integrated circuit structures including a titanium silicide material Jun 24, 2020 Issued
Array ( [id] => 19330477 [patent_doc_number] => 12048177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-23 [patent_title] => OLED light-emitting device, method for preparing OLED light-emitting device, and lamp [patent_app_type] => utility [patent_app_number] => 17/425190 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6321 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17425190 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/425190
OLED light-emitting device, method for preparing OLED light-emitting device, and lamp Jun 22, 2020 Issued
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