
Christine A. Enad
Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )
| Most Active Art Unit | 2811 |
| Art Unit(s) | 2823, 2811, 4116 |
| Total Applications | 1524 |
| Issued Applications | 1218 |
| Pending Applications | 124 |
| Abandoned Applications | 210 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16316392
[patent_doc_number] => 20200295130
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-17
[patent_title] => NANOSHEET TRANSISTOR BOTTOM ISOLATION
[patent_app_type] => utility
[patent_app_number] => 16/353447
[patent_app_country] => US
[patent_app_date] => 2019-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5672
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 48
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16353447
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/353447 | Nanosheet transistor bottom isolation | Mar 13, 2019 | Issued |
Array
(
[id] => 14509685
[patent_doc_number] => 20190198497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-27
[patent_title] => INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/288727
[patent_app_country] => US
[patent_app_date] => 2019-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13660
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 145
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16288727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/288727 | Integrated circuit device and method of manufacturing the same | Feb 27, 2019 | Issued |
Array
(
[id] => 16021003
[patent_doc_number] => 20200185345
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-11
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/283292
[patent_app_country] => US
[patent_app_date] => 2019-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6405
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16283292
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/283292 | SEMICONDUCTOR DEVICE | Feb 21, 2019 | Abandoned |
Array
(
[id] => 18120705
[patent_doc_number] => 11552104
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Stacked transistors with dielectric between channels of different device strata
[patent_app_type] => utility
[patent_app_number] => 16/279693
[patent_app_country] => US
[patent_app_date] => 2019-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 41
[patent_no_of_words] => 13598
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279693
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/279693 | Stacked transistors with dielectric between channels of different device strata | Feb 18, 2019 | Issued |
Array
(
[id] => 14667577
[patent_doc_number] => 10371684
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-08-06
[patent_title] => Sealed container sensor device
[patent_app_type] => utility
[patent_app_number] => 16/278401
[patent_app_country] => US
[patent_app_date] => 2019-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 15109
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16278401
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/278401 | Sealed container sensor device | Feb 17, 2019 | Issued |
Array
(
[id] => 14446531
[patent_doc_number] => 20190181139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-13
[patent_title] => VERTICAL FET WITH REDUCED PARASITIC CAPACITANCE
[patent_app_type] => utility
[patent_app_number] => 16/276133
[patent_app_country] => US
[patent_app_date] => 2019-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5432
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16276133
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/276133 | Vertical FET with reduced parasitic capacitance | Feb 13, 2019 | Issued |
Array
(
[id] => 16241842
[patent_doc_number] => 20200259076
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => Heusler Compounds with Non-Magnetic Spacer Layer for Formation of Synthetic Anti-Ferromagnets (SAF)
[patent_app_type] => utility
[patent_app_number] => 16/271721
[patent_app_country] => US
[patent_app_date] => 2019-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5253
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -31
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271721
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/271721 | Heusler compounds with non-magnetic spacer layer for formation of synthetic anti-ferromagnets (SAF) | Feb 7, 2019 | Issued |
Array
(
[id] => 14413997
[patent_doc_number] => 20190172842
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-06
[patent_title] => TRANSISTOR FINGER SPACING AND DIMENSION VARIATION IN ELECTRONIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/270946
[patent_app_country] => US
[patent_app_date] => 2019-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16624
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270946
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/270946 | Transistor finger spacing and dimension variation in electronic devices | Feb 7, 2019 | Issued |
Array
(
[id] => 16241707
[patent_doc_number] => 20200258941
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-08-13
[patent_title] => VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS COMBINED WITH RESISTIVE MEMORY STRUCTURES
[patent_app_type] => utility
[patent_app_number] => 16/271501
[patent_app_country] => US
[patent_app_date] => 2019-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8616
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271501
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/271501 | Vertical transport Fin field effect transistors combined with resistive memory structures | Feb 7, 2019 | Issued |
Array
(
[id] => 14476309
[patent_doc_number] => 20190189803
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-20
[patent_title] => SELECTIVE DEPOSITION UTILIZING SACRIFICIAL BLOCKING LAYERS FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/271226
[patent_app_country] => US
[patent_app_date] => 2019-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9438
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16271226
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/271226 | Selective deposition utilizing sacrificial blocking layers for semiconductor devices | Feb 7, 2019 | Issued |
Array
(
[id] => 15260305
[patent_doc_number] => 20190378886
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-12
[patent_title] => ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/270072
[patent_app_country] => US
[patent_app_date] => 2019-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8885
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16270072
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/270072 | Organic light-emitting diode display device | Feb 6, 2019 | Issued |
Array
(
[id] => 16739014
[patent_doc_number] => 10964680
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Display device
[patent_app_type] => utility
[patent_app_number] => 16/262607
[patent_app_country] => US
[patent_app_date] => 2019-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 8555
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262607
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/262607 | Display device | Jan 29, 2019 | Issued |
Array
(
[id] => 17254202
[patent_doc_number] => 11189702
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-30
[patent_title] => Split gate semiconductor with non-uniform trench oxide
[patent_app_type] => utility
[patent_app_number] => 16/262598
[patent_app_country] => US
[patent_app_date] => 2019-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7479
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262598
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/262598 | Split gate semiconductor with non-uniform trench oxide | Jan 29, 2019 | Issued |
Array
(
[id] => 15922061
[patent_doc_number] => 10658279
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-19
[patent_title] => High density package interconnects
[patent_app_type] => utility
[patent_app_number] => 16/261475
[patent_app_country] => US
[patent_app_date] => 2019-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 18
[patent_no_of_words] => 5976
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16261475
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/261475 | High density package interconnects | Jan 28, 2019 | Issued |
Array
(
[id] => 18460735
[patent_doc_number] => 11685015
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Method and system for performing chemical mechanical polishing
[patent_app_type] => utility
[patent_app_number] => 16/259856
[patent_app_country] => US
[patent_app_date] => 2019-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 45
[patent_no_of_words] => 10854
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16259856
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/259856 | Method and system for performing chemical mechanical polishing | Jan 27, 2019 | Issued |
Array
(
[id] => 16560507
[patent_doc_number] => 20210005656
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-07
[patent_title] => IMAGING ELEMENT AND METHOD OF MANUFACTURING IMAGING ELEMENT
[patent_app_type] => utility
[patent_app_number] => 16/976749
[patent_app_country] => US
[patent_app_date] => 2019-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9178
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16976749
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/976749 | Imaging element and method of manufacturing imaging element | Jan 20, 2019 | Issued |
Array
(
[id] => 16180470
[patent_doc_number] => 20200227439
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-07-16
[patent_title] => THREE-DIMENSIONAL FERROELECTRIC MEMORY DEVICES INCLUDING A BACKSIDE GATE ELECTRODE AND METHODS OF MAKING SAME
[patent_app_type] => utility
[patent_app_number] => 16/249300
[patent_app_country] => US
[patent_app_date] => 2019-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23342
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249300
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/249300 | Three-dimensional ferroelectric memory devices including a backside gate electrode and methods of making same | Jan 15, 2019 | Issued |
Array
(
[id] => 14588213
[patent_doc_number] => 20190221715
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/249302
[patent_app_country] => US
[patent_app_date] => 2019-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4831
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249302
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/249302 | Semiconductor light emitting device and method of manufacturing semiconductor light emitting device | Jan 15, 2019 | Issued |
Array
(
[id] => 14588213
[patent_doc_number] => 20190221715
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-18
[patent_title] => SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/249302
[patent_app_country] => US
[patent_app_date] => 2019-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4831
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249302
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/249302 | Semiconductor light emitting device and method of manufacturing semiconductor light emitting device | Jan 15, 2019 | Issued |
Array
(
[id] => 15274361
[patent_doc_number] => 20190385915
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-19
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/249353
[patent_app_country] => US
[patent_app_date] => 2019-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6565
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249353
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/249353 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | Jan 15, 2019 | Abandoned |