Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14367081 [patent_doc_number] => 10304853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-28 [patent_title] => Memory arrays, and methods of forming memory arrays [patent_app_type] => utility [patent_app_number] => 16/031919 [patent_app_country] => US [patent_app_date] => 2018-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5355 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16031919 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/031919
Memory arrays, and methods of forming memory arrays Jul 9, 2018 Issued
Array ( [id] => 15061753 [patent_doc_number] => 10461189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Fin field effect transistors having liners between device isolation layers and active areas of the device [patent_app_type] => utility [patent_app_number] => 16/028918 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 18116 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16028918 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/028918
Fin field effect transistors having liners between device isolation layers and active areas of the device Jul 5, 2018 Issued
Array ( [id] => 14459691 [patent_doc_number] => 10325817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors [patent_app_type] => utility [patent_app_number] => 16/018921 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018921 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/018921
Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors Jun 25, 2018 Issued
Array ( [id] => 13499817 [patent_doc_number] => 20180301451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-18 [patent_title] => VERTICAL FET WITH REDUCED PARASITIC CAPACITANCE [patent_app_type] => utility [patent_app_number] => 16/005124 [patent_app_country] => US [patent_app_date] => 2018-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5432 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16005124 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/005124
Vertical FET with reduced parasitic capacitance Jun 10, 2018 Issued
Array ( [id] => 15547675 [patent_doc_number] => 10573628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-25 [patent_title] => Light emitting device [patent_app_type] => utility [patent_app_number] => 15/971196 [patent_app_country] => US [patent_app_date] => 2018-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 10760 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15971196 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/971196
Light emitting device May 3, 2018 Issued
Array ( [id] => 16218521 [patent_doc_number] => 10734343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Method and system for packing optimization of semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/968360 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 8764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968360 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968360
Method and system for packing optimization of semiconductor devices Apr 30, 2018 Issued
Array ( [id] => 13392989 [patent_doc_number] => 20180248037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => VERTICAL FET STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/964487 [patent_app_country] => US [patent_app_date] => 2018-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15964487 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/964487
Vertical FET structure Apr 26, 2018 Issued
Array ( [id] => 17174477 [patent_doc_number] => 20210328148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-21 [patent_title] => SEMICONDUCTOR MIXED MATERIAL AND MANUFACTURING METHOD THEREOF, THIN FILM TRANSISTOR AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 16/328423 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16328423 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/328423
SEMICONDUCTOR MIXED MATERIAL AND MANUFACTURING METHOD THEREOF, THIN FILM TRANSISTOR AND ELECTRONIC DEVICE Apr 22, 2018 Abandoned
Array ( [id] => 17239557 [patent_doc_number] => 11183448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-23 [patent_title] => Wiring circuit board and imaging device [patent_app_type] => utility [patent_app_number] => 16/607612 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 37 [patent_no_of_words] => 15505 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16607612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/607612
Wiring circuit board and imaging device Apr 22, 2018 Issued
Array ( [id] => 15611359 [patent_doc_number] => 10586749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => High power gallium nitride devices and structures [patent_app_type] => utility [patent_app_number] => 15/960508 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5847 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960508
High power gallium nitride devices and structures Apr 22, 2018 Issued
Array ( [id] => 14617123 [patent_doc_number] => 10361269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Forming bottom isolation layer for nanosheet technology [patent_app_type] => utility [patent_app_number] => 15/946768 [patent_app_country] => US [patent_app_date] => 2018-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 43 [patent_no_of_words] => 5176 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15946768 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/946768
Forming bottom isolation layer for nanosheet technology Apr 5, 2018 Issued
Array ( [id] => 13528511 [patent_doc_number] => 20180315798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => PHOTODETECTOR [patent_app_type] => utility [patent_app_number] => 15/945790 [patent_app_country] => US [patent_app_date] => 2018-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19451 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15945790 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/945790
Photodetector Apr 4, 2018 Issued
Array ( [id] => 13335019 [patent_doc_number] => 20180219047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-02 [patent_title] => PHOTOSENSOR [patent_app_type] => utility [patent_app_number] => 15/939381 [patent_app_country] => US [patent_app_date] => 2018-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15939381 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/939381
Photosensor Mar 28, 2018 Issued
Array ( [id] => 14985421 [patent_doc_number] => 10446632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Organic light-emitting diode display panel [patent_app_type] => utility [patent_app_number] => 15/938997 [patent_app_country] => US [patent_app_date] => 2018-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15938997 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/938997
Organic light-emitting diode display panel Mar 27, 2018 Issued
Array ( [id] => 13976999 [patent_doc_number] => 10217869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Semiconductor structure including low-K spacer material [patent_app_type] => utility [patent_app_number] => 15/936149 [patent_app_country] => US [patent_app_date] => 2018-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3890 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15936149 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/936149
Semiconductor structure including low-K spacer material Mar 25, 2018 Issued
Array ( [id] => 14382785 [patent_doc_number] => 20190165305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 15/928604 [patent_app_country] => US [patent_app_date] => 2018-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15928604 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/928604
OLED DISPLAY PANEL AND MANUFACTURING METHOD THEREOF Mar 21, 2018 Abandoned
Array ( [id] => 14191693 [patent_doc_number] => 20190115552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => OLED PANEL, OLED DISPLAY AND MANUFACTURING METHOD OF OLED PANEL [patent_app_type] => utility [patent_app_number] => 15/925179 [patent_app_country] => US [patent_app_date] => 2018-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2846 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15925179 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/925179
OLED panel, OLED display and manufacturing method of OLED panel Mar 18, 2018 Issued
Array ( [id] => 14397885 [patent_doc_number] => 10312234 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Diode connected vertical transistor [patent_app_type] => utility [patent_app_number] => 15/907908 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 10265 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15907908 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/907908
Diode connected vertical transistor Feb 27, 2018 Issued
Array ( [id] => 15331439 [patent_doc_number] => 20200006049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-02 [patent_title] => METHOD FOR MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE AND NITRIDE SEMICONDUCTOR SUBSTRATE [patent_app_type] => utility [patent_app_number] => 16/490704 [patent_app_country] => US [patent_app_date] => 2018-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12123 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16490704 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/490704
Method for manufacturing nitride semiconductor substrate and nitride semiconductor substrate Feb 27, 2018 Issued
Array ( [id] => 12872563 [patent_doc_number] => 20180182696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => HIGH DENSITY PACKAGE INTERCONNECTS [patent_app_type] => utility [patent_app_number] => 15/900696 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5892 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900696 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900696
High density package interconnects Feb 19, 2018 Issued
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