Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12650802 [patent_doc_number] => 20180108765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 15/837318 [patent_app_country] => US [patent_app_date] => 2017-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11373 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15837318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/837318
Semiconductor device and method for producing the same Dec 10, 2017 Issued
Array ( [id] => 13435323 [patent_doc_number] => 20180269204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => DIODE CONNECTED VERTICAL TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/830497 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10264 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830497 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/830497
Diode connected vertical transistor Dec 3, 2017 Issued
Array ( [id] => 16293633 [patent_doc_number] => 10770488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Active switch array substrate and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/317045 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4854 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16317045 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/317045
Active switch array substrate and method for manufacturing the same Dec 3, 2017 Issued
Array ( [id] => 12824257 [patent_doc_number] => 20180166591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => PHOTOELECTRIC CONVERSION DEVICE, METHOD OF MANUFACTURING THE SAME, AND CAMERA [patent_app_type] => utility [patent_app_number] => 15/825443 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825443 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825443
Photoelectric conversion device, method of manufacturing the same, and camera Nov 28, 2017 Issued
Array ( [id] => 14617207 [patent_doc_number] => 10361311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Semiconductor structure including low-k spacer material [patent_app_type] => utility [patent_app_number] => 15/825409 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3889 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825409 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825409
Semiconductor structure including low-k spacer material Nov 28, 2017 Issued
Array ( [id] => 14191667 [patent_doc_number] => 20190115539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => ORGANIC LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 15/826631 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15826631 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/826631
ORGANIC LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME Nov 28, 2017 Abandoned
Array ( [id] => 17332562 [patent_doc_number] => 11223032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-11 [patent_title] => Thin film barrier structure [patent_app_type] => utility [patent_app_number] => 15/825493 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 9531 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15825493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/825493
Thin film barrier structure Nov 28, 2017 Issued
Array ( [id] => 15046161 [patent_doc_number] => 20190334085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => METHOD FOR MANUFACTURING A RESISTIVE MEMORY [patent_app_type] => utility [patent_app_number] => 16/462058 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16462058 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/462058
Method for manufacturing a resistive memory Nov 15, 2017 Issued
Array ( [id] => 16812333 [patent_doc_number] => 20210134888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => DISPLAY PANEL, METHOD FOR FABRICATING THE SAME, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/775251 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5820 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15775251 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/775251
Display panel, method for fabricating the same, and display device Nov 15, 2017 Issued
Array ( [id] => 13111989 [patent_doc_number] => 10074652 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-09-11 [patent_title] => Vertical FET with reduced parasitic capacitance [patent_app_type] => utility [patent_app_number] => 15/808124 [patent_app_country] => US [patent_app_date] => 2017-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 5430 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15808124 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/808124
Vertical FET with reduced parasitic capacitance Nov 8, 2017 Issued
Array ( [id] => 12396336 [patent_doc_number] => 09966369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Light emitting device package [patent_app_type] => utility [patent_app_number] => 15/802493 [patent_app_country] => US [patent_app_date] => 2017-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 10750 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15802493 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/802493
Light emitting device package Nov 2, 2017 Issued
Array ( [id] => 14267863 [patent_doc_number] => 10283503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Metal gate structure and methods thereof [patent_app_type] => utility [patent_app_number] => 15/799555 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 7662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799555 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799555
Metal gate structure and methods thereof Oct 30, 2017 Issued
Array ( [id] => 16067615 [patent_doc_number] => 10692769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Fin critical dimension loading optimization [patent_app_type] => utility [patent_app_number] => 15/799611 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799611
Fin critical dimension loading optimization Oct 30, 2017 Issued
Array ( [id] => 14238523 [patent_doc_number] => 20190131434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-02 [patent_title] => FIN FIELD-EFFECT TRANSISTORS AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/799344 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9566 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799344 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799344
Fin field-effect transistors and methods of forming the same Oct 30, 2017 Issued
Array ( [id] => 16067615 [patent_doc_number] => 10692769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Fin critical dimension loading optimization [patent_app_type] => utility [patent_app_number] => 15/799611 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799611
Fin critical dimension loading optimization Oct 30, 2017 Issued
Array ( [id] => 16067615 [patent_doc_number] => 10692769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Fin critical dimension loading optimization [patent_app_type] => utility [patent_app_number] => 15/799611 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799611
Fin critical dimension loading optimization Oct 30, 2017 Issued
Array ( [id] => 16067615 [patent_doc_number] => 10692769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Fin critical dimension loading optimization [patent_app_type] => utility [patent_app_number] => 15/799611 [patent_app_country] => US [patent_app_date] => 2017-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15799611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/799611
Fin critical dimension loading optimization Oct 30, 2017 Issued
Array ( [id] => 13976893 [patent_doc_number] => 10217815 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Integrated circuit device with source/drain barrier [patent_app_type] => utility [patent_app_number] => 15/796968 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796968 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796968
Integrated circuit device with source/drain barrier Oct 29, 2017 Issued
Array ( [id] => 12188810 [patent_doc_number] => 20180047746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-15 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/797637 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 23136 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797637 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797637
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME Oct 29, 2017 Abandoned
Array ( [id] => 13976551 [patent_doc_number] => 10217640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Methods of fabricating semiconductor devices [patent_app_type] => utility [patent_app_number] => 15/797340 [patent_app_country] => US [patent_app_date] => 2017-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 5888 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15797340 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/797340
Methods of fabricating semiconductor devices Oct 29, 2017 Issued
Menu