Search

Christine A. Enad

Examiner (ID: 4019, Phone: (571)270-7891 , Office: P/2823 )

Most Active Art Unit
2811
Art Unit(s)
2823, 2811, 4116
Total Applications
1524
Issued Applications
1218
Pending Applications
124
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13159703 [patent_doc_number] => 10096587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Fin-based diode structures with a realigned feature layout [patent_app_type] => utility [patent_app_number] => 15/794688 [patent_app_country] => US [patent_app_date] => 2017-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15794688 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/794688
Fin-based diode structures with a realigned feature layout Oct 25, 2017 Issued
Array ( [id] => 14221765 [patent_doc_number] => 20190123267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => Multiple Hard Mask Patterning to Fabricate 20nm and Below MRAM Devices [patent_app_type] => utility [patent_app_number] => 15/790649 [patent_app_country] => US [patent_app_date] => 2017-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1761 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15790649 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/790649
Multiple hard mask patterning to fabricate 20nm and below MRAM devices Oct 22, 2017 Issued
Array ( [id] => 13159581 [patent_doc_number] => 10096524 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-10-09 [patent_title] => Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors [patent_app_type] => utility [patent_app_number] => 15/786744 [patent_app_country] => US [patent_app_date] => 2017-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 6650 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15786744 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/786744
Semiconductor fin patterning techniques to achieve uniform fin profiles for fin field effect transistors Oct 17, 2017 Issued
Array ( [id] => 12823399 [patent_doc_number] => 20180166305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => METHOD AND APPARATUS FOR WAFER BACKSIDE COOLING [patent_app_type] => utility [patent_app_number] => 15/729841 [patent_app_country] => US [patent_app_date] => 2017-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3923 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729841 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/729841
Method and apparatus for wafer backside cooling Oct 10, 2017 Issued
Array ( [id] => 13031025 [patent_doc_number] => 10038138 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-31 [patent_title] => High temperature volatilization of sidewall materials from patterned magnetic tunnel junctions [patent_app_type] => utility [patent_app_number] => 15/728839 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 6641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728839 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/728839
High temperature volatilization of sidewall materials from patterned magnetic tunnel junctions Oct 9, 2017 Issued
Array ( [id] => 16233847 [patent_doc_number] => 10741410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Material composition and methods thereof [patent_app_type] => utility [patent_app_number] => 15/726040 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 31 [patent_no_of_words] => 7184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15726040 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/726040
Material composition and methods thereof Oct 4, 2017 Issued
Array ( [id] => 12181554 [patent_doc_number] => 20180040490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/724744 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5246 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724744 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724744
Manufacturing method of semiconductor device and semiconductor manufacturing apparatus Oct 3, 2017 Issued
Array ( [id] => 12615225 [patent_doc_number] => 20180096905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-05 [patent_title] => FACILITATION OF SPIN-COAT PLANARIZATION OVER FEATURE TOPOGRAPHY DURING SUBSTRATE FABRICATION [patent_app_type] => utility [patent_app_number] => 15/724632 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7869 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724632 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724632
Facilitation of spin-coat planarization over feature topography during substrate fabrication Oct 3, 2017 Issued
Array ( [id] => 16293631 [patent_doc_number] => 10770486 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-08 [patent_title] => Method of producing liquid crystal cell, and liquid crystal cell [patent_app_type] => utility [patent_app_number] => 16/339415 [patent_app_country] => US [patent_app_date] => 2017-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 11905 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16339415 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/339415
Method of producing liquid crystal cell, and liquid crystal cell Oct 1, 2017 Issued
Array ( [id] => 15376063 [patent_doc_number] => 10529760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Solid-state imaging device, method of manufacturing the same, and electronic equipment [patent_app_type] => utility [patent_app_number] => 15/719097 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 12390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15719097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/719097
Solid-state imaging device, method of manufacturing the same, and electronic equipment Sep 27, 2017 Issued
Array ( [id] => 17941895 [patent_doc_number] => 11476357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-18 [patent_title] => Semiconductor device comprising a three-dimensional field plate [patent_app_type] => utility [patent_app_number] => 16/337668 [patent_app_country] => US [patent_app_date] => 2017-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 56 [patent_no_of_words] => 7754 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16337668 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/337668
Semiconductor device comprising a three-dimensional field plate Sep 27, 2017 Issued
Array ( [id] => 13283565 [patent_doc_number] => 10153374 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/715100 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4905 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15715100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/715100
Semiconductor device and manufacturing method thereof Sep 24, 2017 Issued
Array ( [id] => 14036351 [patent_doc_number] => 10229932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Voltage distribution in transistor stacks using non-uniform transistor dimensions [patent_app_type] => utility [patent_app_number] => 15/714221 [patent_app_country] => US [patent_app_date] => 2017-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 51 [patent_no_of_words] => 16598 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15714221 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/714221
Voltage distribution in transistor stacks using non-uniform transistor dimensions Sep 24, 2017 Issued
Array ( [id] => 15185123 [patent_doc_number] => 20190363153 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/466808 [patent_app_country] => US [patent_app_date] => 2017-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16466808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/466808
Display device Sep 21, 2017 Issued
Array ( [id] => 12122612 [patent_doc_number] => 20180006198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-04 [patent_title] => 'LIGHT EMITTING DIODE CHIP HAVING WAVELENGTH CONVERTING LAYER AND METHOD OF FABRICATING THE SAME, AND PACKAGE HAVING THE LIGHT EMITTING DIODE CHIP AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/703725 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14715 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703725 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703725
Light emitting diode chip having wavelength converting layer and method of fabricating the same, and package having the light emitting diode chip and method of fabricating the same Sep 12, 2017 Issued
Array ( [id] => 12436656 [patent_doc_number] => 09978736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-22 [patent_title] => Method for manufacturing memory having stacked integrated circuit chip [patent_app_type] => utility [patent_app_number] => 15/703144 [patent_app_country] => US [patent_app_date] => 2017-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4514 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15703144 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/703144
Method for manufacturing memory having stacked integrated circuit chip Sep 12, 2017 Issued
Array ( [id] => 12595656 [patent_doc_number] => 20180090382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/687444 [patent_app_country] => US [patent_app_date] => 2017-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 519 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15687444 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/687444
Manufacturing method of semiconductor device Aug 25, 2017 Issued
Array ( [id] => 12223272 [patent_doc_number] => 20180061632 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-01 [patent_title] => 'PROCESS OF FORMING NITRIDE SEMICONDUCTOR LAYERS' [patent_app_type] => utility [patent_app_number] => 15/686755 [patent_app_country] => US [patent_app_date] => 2017-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686755 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686755
Process of forming nitride semiconductor layers Aug 24, 2017 Issued
Array ( [id] => 12095675 [patent_doc_number] => 20170352768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'SEMICONDUCTOR DEVICE MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 15/686148 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18200 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15686148 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/686148
Semiconductor device manufacturing method Aug 23, 2017 Issued
Array ( [id] => 13995753 [patent_doc_number] => 20190067034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND [patent_app_type] => utility [patent_app_number] => 15/685940 [patent_app_country] => US [patent_app_date] => 2017-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6937 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15685940 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/685940
HYBRID ADDITIVE STRUCTURE STACKABLE MEMORY DIE USING WIRE BOND Aug 23, 2017 Abandoned
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