Search

Christine T. Duong

Examiner (ID: 2346)

Most Active Art Unit
2462
Art Unit(s)
2416, 2462, 2616
Total Applications
777
Issued Applications
656
Pending Applications
10
Abandoned Applications
123

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15580621 [patent_doc_number] => 10580703 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Multivalent oxide cap for multiple work function gate stacks on high mobility channel materials [patent_app_type] => utility [patent_app_number] => 15/969252 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5250 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15969252 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/969252
Multivalent oxide cap for multiple work function gate stacks on high mobility channel materials May 1, 2018 Issued
Array ( [id] => 13543345 [patent_doc_number] => 20180323219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-08 [patent_title] => ACTIVE DEVICE ARRAY STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/968722 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 276 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968722 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968722
Active device array structure Apr 30, 2018 Issued
Array ( [id] => 15315585 [patent_doc_number] => 10522508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Semiconductor device package and a method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/968562 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 15246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968562
Semiconductor device package and a method of manufacturing the same Apr 30, 2018 Issued
Array ( [id] => 15139883 [patent_doc_number] => 10483430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => Micron-sized light emitting diode designs [patent_app_type] => utility [patent_app_number] => 15/968359 [patent_app_country] => US [patent_app_date] => 2018-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 10021 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968359 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/968359
Micron-sized light emitting diode designs Apr 30, 2018 Issued
Array ( [id] => 13405589 [patent_doc_number] => 20180254337 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-06 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/966879 [patent_app_country] => US [patent_app_date] => 2018-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5271 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15966879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/966879
Semiconductor device Apr 29, 2018 Issued
Array ( [id] => 16495874 [patent_doc_number] => 10861926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-08 [patent_title] => Display substrate, display apparatus, and fabricating method thereof [patent_app_type] => utility [patent_app_number] => 16/303340 [patent_app_country] => US [patent_app_date] => 2018-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 8002 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16303340 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/303340
Display substrate, display apparatus, and fabricating method thereof Apr 25, 2018 Issued
Array ( [id] => 13528375 [patent_doc_number] => 20180315730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => BACKSIDE METALIZATION WITH THROUGH-WAFER-VIA PROCESSING TO ALLOW USE OF HIGH Q BONDWIRE INDUCTANCES [patent_app_type] => utility [patent_app_number] => 15/958152 [patent_app_country] => US [patent_app_date] => 2018-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5340 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15958152 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/958152
Backside metalization with through-wafer-via processing to allow use of high q bondwire inductances Apr 19, 2018 Issued
Array ( [id] => 14125683 [patent_doc_number] => 10249706 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-02 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 15/951185 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2878 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951185 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951185
Semiconductor structure Apr 11, 2018 Issued
Array ( [id] => 15526841 [patent_doc_number] => 20200055726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-20 [patent_title] => MEMS DEVICE [patent_app_type] => utility [patent_app_number] => 16/603740 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9808 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16603740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/603740
MEMS device Apr 11, 2018 Issued
Array ( [id] => 14558111 [patent_doc_number] => 10347526 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-07-09 [patent_title] => Semiconductor structure and method for forming the same [patent_app_type] => utility [patent_app_number] => 15/951683 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 4372 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951683 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951683
Semiconductor structure and method for forming the same Apr 11, 2018 Issued
Array ( [id] => 14301193 [patent_doc_number] => 10290730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-05-14 [patent_title] => Semiconductor power device [patent_app_type] => utility [patent_app_number] => 15/951184 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6538 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951184 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951184
Semiconductor power device Apr 11, 2018 Issued
Array ( [id] => 13629669 [patent_doc_number] => 20180366387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-20 [patent_title] => CHIP PACKAGE AND CHIP PACKAGING METHOD [patent_app_type] => utility [patent_app_number] => 15/950302 [patent_app_country] => US [patent_app_date] => 2018-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6199 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15950302 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/950302
Chip package and chip packaging method Apr 10, 2018 Issued
Array ( [id] => 14024551 [patent_doc_number] => 20190074269 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => ELECTRONIC COMPONENT [patent_app_type] => utility [patent_app_number] => 15/949212 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1062 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949212
Electronic component Apr 9, 2018 Issued
Array ( [id] => 14843187 [patent_doc_number] => 20190279994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 15/949368 [patent_app_country] => US [patent_app_date] => 2018-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3050 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15949368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/949368
Semiconductor structure and method for forming the same Apr 9, 2018 Issued
Array ( [id] => 14969013 [patent_doc_number] => 20190311985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => ADVANCED INTERCONNECTS CONTAINING AN IMT LINER [patent_app_type] => utility [patent_app_number] => 15/948809 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948809 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948809
Advanced interconnects containing an IMT liner Apr 8, 2018 Issued
Array ( [id] => 14492103 [patent_doc_number] => 10332852 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-25 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/947933 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3808 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15947933 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/947933
Semiconductor device Apr 8, 2018 Issued
Array ( [id] => 13976965 [patent_doc_number] => 10217852 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-26 [patent_title] => Heterojunction bipolar transistors with a controlled undercut formed beneath the extrinsic base [patent_app_type] => utility [patent_app_number] => 15/948486 [patent_app_country] => US [patent_app_date] => 2018-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15948486 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/948486
Heterojunction bipolar transistors with a controlled undercut formed beneath the extrinsic base Apr 8, 2018 Issued
Array ( [id] => 14459771 [patent_doc_number] => 10325859 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-18 [patent_title] => Shielded stacked substrate apparatus and method of fabricating [patent_app_type] => utility [patent_app_number] => 15/944233 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4562 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944233 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944233
Shielded stacked substrate apparatus and method of fabricating Apr 2, 2018 Issued
Array ( [id] => 15984711 [patent_doc_number] => 10672693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Integrated circuit structures in package substrates [patent_app_type] => utility [patent_app_number] => 15/944728 [patent_app_country] => US [patent_app_date] => 2018-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 18 [patent_no_of_words] => 12207 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944728 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/944728
Integrated circuit structures in package substrates Apr 2, 2018 Issued
Array ( [id] => 14938447 [patent_doc_number] => 20190304862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 15/943334 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15943334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/943334
Semiconductor package Apr 1, 2018 Issued
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