Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14906013 [patent_doc_number] => 20190296772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => PARALLEL BIT INTERLEAVER [patent_app_type] => utility [patent_app_number] => 16/437307 [patent_app_country] => US [patent_app_date] => 2019-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16437307 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/437307
Parallel bit interleaver Jun 10, 2019 Issued
Array ( [id] => 17084118 [patent_doc_number] => 20210279124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => MEMORY SCANNING OPERATION IN RESPONSE TO COMMON MODE FAULT SIGNAL [patent_app_type] => utility [patent_app_number] => 17/261217 [patent_app_country] => US [patent_app_date] => 2019-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7723 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17261217 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/261217
Memory scanning operation in response to common mode fault signal Jun 5, 2019 Issued
Array ( [id] => 14718295 [patent_doc_number] => 20190250211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT [patent_app_type] => utility [patent_app_number] => 16/393352 [patent_app_country] => US [patent_app_date] => 2019-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 40683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16393352 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/393352
Functional, tap, trace circuitry with multiplexed tap, trace data output Apr 23, 2019 Issued
Array ( [id] => 14724251 [patent_doc_number] => 20190253189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => TRANSMISSION METHOD, TRANSMISSION DEVICE, RECEPTION METHOD, AND RECEPTION DEVICE [patent_app_type] => utility [patent_app_number] => 16/391939 [patent_app_country] => US [patent_app_date] => 2019-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26598 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391939 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/391939
Transmission method, transmission device, reception method, and reception device Apr 22, 2019 Issued
Array ( [id] => 14692893 [patent_doc_number] => 20190245562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-08 [patent_title] => PARALLEL BIT INTERLEAVER [patent_app_type] => utility [patent_app_number] => 16/385218 [patent_app_country] => US [patent_app_date] => 2019-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11043 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385218 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/385218
Parallel bit interleaver Apr 15, 2019 Issued
Array ( [id] => 16234783 [patent_doc_number] => 10742353 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Cross-correlation reduction for control signals [patent_app_type] => utility [patent_app_number] => 16/376895 [patent_app_country] => US [patent_app_date] => 2019-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 24273 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16376895 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/376895
Cross-correlation reduction for control signals Apr 4, 2019 Issued
Array ( [id] => 14940487 [patent_doc_number] => 20190305882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-03 [patent_title] => SCHEDULING FOR LOW-DENSITY PARITY-CHECK CODES [patent_app_type] => utility [patent_app_number] => 16/366997 [patent_app_country] => US [patent_app_date] => 2019-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16366997 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/366997
Scheduling for low-density parity-check codes Mar 26, 2019 Issued
Array ( [id] => 14589485 [patent_doc_number] => 20190222351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => TRANSMISSION METHOD, RECEPTION METHOD, TRANSMITTER, AND RECEIVER [patent_app_type] => utility [patent_app_number] => 16/360221 [patent_app_country] => US [patent_app_date] => 2019-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 162490 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16360221 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/360221
Transmission method, reception method, transmitter, and receiver Mar 20, 2019 Issued
Array ( [id] => 16200701 [patent_doc_number] => 10725864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/352882 [patent_app_country] => US [patent_app_date] => 2019-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 48 [patent_no_of_words] => 27810 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352882 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352882
Memory system Mar 13, 2019 Issued
Array ( [id] => 15027319 [patent_doc_number] => 20190324664 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-24 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD OF THE MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 16/352584 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352584 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352584
Memory system and operating method of the memory system Mar 12, 2019 Issued
Array ( [id] => 16047711 [patent_doc_number] => 10685734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Semiconductor integrated circuit and test method [patent_app_type] => utility [patent_app_number] => 16/294976 [patent_app_country] => US [patent_app_date] => 2019-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5746 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16294976 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/294976
Semiconductor integrated circuit and test method Mar 6, 2019 Issued
Array ( [id] => 16462822 [patent_doc_number] => 10846170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Decoder, operating method thereof and memory system including the decoder [patent_app_type] => utility [patent_app_number] => 16/279530 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 25 [patent_no_of_words] => 12745 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279530 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279530
Decoder, operating method thereof and memory system including the decoder Feb 18, 2019 Issued
Array ( [id] => 16119261 [patent_doc_number] => 20200211653 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => FLASH MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/279046 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5701 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279046 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279046
Flash memory and operation method thereof Feb 18, 2019 Issued
Array ( [id] => 17076746 [patent_doc_number] => 11113145 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Memory device, semiconductor device, and semiconductor system [patent_app_type] => utility [patent_app_number] => 16/279917 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8502 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279917 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279917
Memory device, semiconductor device, and semiconductor system Feb 18, 2019 Issued
Array ( [id] => 16065241 [patent_doc_number] => 10691570 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Software assistant for power-on-self-test (POST) and built-in self-test (BIST) in in-vehicle network (IVN) of connected vehicles [patent_app_type] => utility [patent_app_number] => 16/279277 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5535 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279277 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279277
Software assistant for power-on-self-test (POST) and built-in self-test (BIST) in in-vehicle network (IVN) of connected vehicles Feb 18, 2019 Issued
Array ( [id] => 16820612 [patent_doc_number] => 11005458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Semiconductor integrated circuit adapted to scan testing, and method of designing the same [patent_app_type] => utility [patent_app_number] => 16/279131 [patent_app_country] => US [patent_app_date] => 2019-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7385 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16279131 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/279131
Semiconductor integrated circuit adapted to scan testing, and method of designing the same Feb 18, 2019 Issued
Array ( [id] => 15151655 [patent_doc_number] => 20190354305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-21 [patent_title] => CODE WORD FORMAT AND STRUCTURE [patent_app_type] => utility [patent_app_number] => 16/249808 [patent_app_country] => US [patent_app_date] => 2019-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12590 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16249808 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/249808
Code word format and structure Jan 15, 2019 Issued
Array ( [id] => 16745174 [patent_doc_number] => 10970164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Storage device and operating method of storage device [patent_app_type] => utility [patent_app_number] => 16/248540 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8420 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248540 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248540
Storage device and operating method of storage device Jan 14, 2019 Issued
Array ( [id] => 16172618 [patent_doc_number] => 10714194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Memory system including a memory device, and methods of operating the memory system and memory device [patent_app_type] => utility [patent_app_number] => 16/248568 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 11818 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248568
Memory system including a memory device, and methods of operating the memory system and memory device Jan 14, 2019 Issued
Array ( [id] => 16433701 [patent_doc_number] => 10833804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-10 [patent_title] => Receiver and method for processing a signal thereof [patent_app_type] => utility [patent_app_number] => 16/241169 [patent_app_country] => US [patent_app_date] => 2019-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 11871 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16241169 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/241169
Receiver and method for processing a signal thereof Jan 6, 2019 Issued
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