Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12250878 [patent_doc_number] => 09923671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Communication device' [patent_app_type] => utility [patent_app_number] => 15/358304 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 8007 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358304 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358304
Communication device Nov 21, 2016 Issued
Array ( [id] => 11500749 [patent_doc_number] => 20170074933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'HIGH SPEED INTERCONNECT CIRCUIT TEST METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/359024 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13717 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15359024 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/359024
High speed interconnect circuit test method and apparatus Nov 21, 2016 Issued
Array ( [id] => 11653540 [patent_doc_number] => 20170149444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'ERROR CORRECTION USING CYCLIC CODE-BASED LDPC CODES' [patent_app_type] => utility [patent_app_number] => 15/357801 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 31448 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357801 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357801
Error correction using cyclic code-based LDPC codes Nov 20, 2016 Issued
Array ( [id] => 11665134 [patent_doc_number] => 20170153853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'LOAD BALANCING AND SERVICE DIFFERENTIATION WITHIN A DISPERSED STORAGE NETWORK' [patent_app_type] => utility [patent_app_number] => 15/356929 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356929 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356929
Load balancing and service differentiation within a dispersed storage network Nov 20, 2016 Issued
Array ( [id] => 12290886 [patent_doc_number] => 09933969 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Securing encoding data slices using an integrity check value list [patent_app_type] => utility [patent_app_number] => 15/357293 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7722 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357293
Securing encoding data slices using an integrity check value list Nov 20, 2016 Issued
Array ( [id] => 14123279 [patent_doc_number] => 10248498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Cyclic redundancy check calculation for multiple blocks of a message [patent_app_type] => utility [patent_app_number] => 15/357296 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7269 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357296 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357296
Cyclic redundancy check calculation for multiple blocks of a message Nov 20, 2016 Issued
Array ( [id] => 11653546 [patent_doc_number] => 20170149452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'Flexible Polynomial-Based Interleaver' [patent_app_type] => utility [patent_app_number] => 15/357382 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8996 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15357382 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/357382
Flexible polynomial-based interleaver Nov 20, 2016 Issued
Array ( [id] => 11660821 [patent_doc_number] => 09673838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-06 [patent_title] => 'Parallel bit interleaver' [patent_app_type] => utility [patent_app_number] => 15/335501 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 103 [patent_no_of_words] => 20644 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15335501 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/335501
Parallel bit interleaver Oct 26, 2016 Issued
Array ( [id] => 11874749 [patent_doc_number] => 09746515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Address-command port connected to trace circuits and tap domains' [patent_app_type] => utility [patent_app_number] => 15/336139 [patent_app_country] => US [patent_app_date] => 2016-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 81 [patent_figures_cnt] => 114 [patent_no_of_words] => 41722 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15336139 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/336139
Address-command port connected to trace circuits and tap domains Oct 26, 2016 Issued
Array ( [id] => 11403742 [patent_doc_number] => 20170024281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-26 [patent_title] => 'FAILURE-DECOUPLED VOLUME-LEVEL REDUNDANCY CODING TECHNIQUES' [patent_app_type] => utility [patent_app_number] => 15/283023 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 15621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15283023 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/283023
Failure-decoupled volume-level redundancy coding techniques Sep 29, 2016 Issued
Array ( [id] => 11398676 [patent_doc_number] => 20170019214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-19 [patent_title] => 'POLAR CODE HYBRID AUTOMATIC REPEAT REQUEST METHOD AND APPARATUS, AND WIRELESS COMMUNICATIONS APPARATUS' [patent_app_type] => utility [patent_app_number] => 15/280546 [patent_app_country] => US [patent_app_date] => 2016-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6205 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15280546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/280546
Polar code hybrid automatic repeat request method and apparatus, and wireless communications apparatus Sep 28, 2016 Issued
Array ( [id] => 12398559 [patent_doc_number] => 09967113 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Reception apparatus performing turbo equalizations [patent_app_type] => utility [patent_app_number] => 15/266328 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3417 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 351 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266328 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/266328
Reception apparatus performing turbo equalizations Sep 14, 2016 Issued
Array ( [id] => 14856883 [patent_doc_number] => 10417169 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-09-17 [patent_title] => Methods and apparatus for high-speed serial interface link assist [patent_app_type] => utility [patent_app_number] => 15/264293 [patent_app_country] => US [patent_app_date] => 2016-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6428 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15264293 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/264293
Methods and apparatus for high-speed serial interface link assist Sep 12, 2016 Issued
Array ( [id] => 15854801 [patent_doc_number] => 10642685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Cache memory and processor system [patent_app_type] => utility [patent_app_number] => 15/262218 [patent_app_country] => US [patent_app_date] => 2016-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 7324 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15262218 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/262218
Cache memory and processor system Sep 11, 2016 Issued
Array ( [id] => 14298713 [patent_doc_number] => 10289483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-14 [patent_title] => Methods and apparatus for embedding an error correction code in storage circuits [patent_app_type] => utility [patent_app_number] => 15/251951 [patent_app_country] => US [patent_app_date] => 2016-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10637 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15251951 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/251951
Methods and apparatus for embedding an error correction code in storage circuits Aug 29, 2016 Issued
Array ( [id] => 13640361 [patent_doc_number] => 09847141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-19 [patent_title] => Classifying memory cells to multiple impairment profiles based on readout bit-flip counts [patent_app_type] => utility [patent_app_number] => 15/225863 [patent_app_country] => US [patent_app_date] => 2016-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7145 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225863 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225863
Classifying memory cells to multiple impairment profiles based on readout bit-flip counts Aug 1, 2016 Issued
Array ( [id] => 14987007 [patent_doc_number] => 10447430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-15 [patent_title] => Forward error correction for streaming data [patent_app_type] => utility [patent_app_number] => 15/225508 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8800 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15225508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/225508
Forward error correction for streaming data Jul 31, 2016 Issued
Array ( [id] => 11630651 [patent_doc_number] => 20170140840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'MEMORY DEVICE AND A MEMORY DEVICE TEST SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/224973 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7613 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224973
Memory device and a memory device test system Jul 31, 2016 Issued
Array ( [id] => 11919133 [patent_doc_number] => 09787331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Decoding path selection device and method' [patent_app_type] => utility [patent_app_number] => 15/224939 [patent_app_country] => US [patent_app_date] => 2016-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 4219 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15224939 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/224939
Decoding path selection device and method Jul 31, 2016 Issued
Array ( [id] => 13379751 [patent_doc_number] => 20180241417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => APPARATUS AND METHOD FOR CREATING AN ASYMMETRIC CHECKSUM [patent_app_type] => utility [patent_app_number] => 15/752321 [patent_app_country] => US [patent_app_date] => 2016-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6922 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15752321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/752321
Apparatus and method for creating an asymmetric checksum Jul 28, 2016 Issued
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