Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10644352 [patent_doc_number] => 09361223 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-07 [patent_title] => 'Storage method and apparatus for random access memory using codeword storage' [patent_app_type] => utility [patent_app_number] => 15/051344 [patent_app_country] => US [patent_app_date] => 2016-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6439 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15051344 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/051344
Storage method and apparatus for random access memory using codeword storage Feb 22, 2016 Issued
Array ( [id] => 11932412 [patent_doc_number] => 09799413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Multi-domain fuse management' [patent_app_type] => utility [patent_app_number] => 15/012721 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5186 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012721 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012721
Multi-domain fuse management Jan 31, 2016 Issued
Array ( [id] => 11027494 [patent_doc_number] => 20160224450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'Memory Built-In Self Test System' [patent_app_type] => utility [patent_app_number] => 15/012707 [patent_app_country] => US [patent_app_date] => 2016-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15012707 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/012707
Memory built-in self test system Jan 31, 2016 Issued
Array ( [id] => 16308489 [patent_doc_number] => 10777294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => DRAM-level error injection and tracking [patent_app_type] => utility [patent_app_number] => 16/066110 [patent_app_country] => US [patent_app_date] => 2016-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4662 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16066110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/066110
DRAM-level error injection and tracking Jan 25, 2016 Issued
Array ( [id] => 16801336 [patent_doc_number] => 10996269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-04 [patent_title] => Adapting the usage configuration of integrated circuit input-output pads [patent_app_type] => utility [patent_app_number] => 15/533479 [patent_app_country] => US [patent_app_date] => 2015-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 7945 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15533479 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/533479
Adapting the usage configuration of integrated circuit input-output pads Dec 21, 2015 Issued
Array ( [id] => 11695211 [patent_doc_number] => 20170170929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-15 [patent_title] => 'SYSTEM AND METHOD TO REQUEST A PORTION OF A MEDIA CONTENT ITEM' [patent_app_type] => utility [patent_app_number] => 14/969849 [patent_app_country] => US [patent_app_date] => 2015-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8727 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14969849 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/969849
System and method to request a portion of a media content item Dec 14, 2015 Issued
Array ( [id] => 11564408 [patent_doc_number] => 09627000 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-04-18 [patent_title] => 'Canary testing for storage devices' [patent_app_type] => utility [patent_app_number] => 14/968551 [patent_app_country] => US [patent_app_date] => 2015-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14968551 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/968551
Canary testing for storage devices Dec 13, 2015 Issued
Array ( [id] => 11078006 [patent_doc_number] => 20160274969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-22 [patent_title] => 'Method and System for Determining Soft Information Offsets' [patent_app_type] => utility [patent_app_number] => 14/965578 [patent_app_country] => US [patent_app_date] => 2015-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18949 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14965578 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/965578
Method and system for determining soft information offsets Dec 9, 2015 Issued
Array ( [id] => 10629846 [patent_doc_number] => 09347994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Boundary scan with coarse and fine delay register clock circuitry' [patent_app_type] => utility [patent_app_number] => 14/962623 [patent_app_country] => US [patent_app_date] => 2015-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 42 [patent_no_of_words] => 13673 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/962623
Boundary scan with coarse and fine delay register clock circuitry Dec 7, 2015 Issued
Array ( [id] => 11671622 [patent_doc_number] => 20170160343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'Systems and Methods for SerDes Physical Layer Qualification and Mitigation' [patent_app_type] => utility [patent_app_number] => 14/959873 [patent_app_country] => US [patent_app_date] => 2015-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7673 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14959873 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/959873
Systems and methods for SerDes physical layer qualification and mitigation Dec 3, 2015 Issued
Array ( [id] => 10733851 [patent_doc_number] => 20160080001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'MULTIPLE SIZE AND RATE FORWARD ERROR CORRECTION (FEC) CODE COMBINATION WITH MINIMUM SHORTENING AND MAXIMUM COMBINED CODE RATE' [patent_app_type] => utility [patent_app_number] => 14/949348 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13795 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949348 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949348
Multiple size and rate forward error correction (FEC) code combination with minimum shortening and maximum combined code rate Nov 22, 2015 Issued
Array ( [id] => 10731007 [patent_doc_number] => 20160077157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS' [patent_app_type] => utility [patent_app_number] => 14/948612 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 183 [patent_figures_cnt] => 183 [patent_no_of_words] => 67612 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14948612 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/948612
Transporting ordered test data, mode select, ready, precharge packet bits Nov 22, 2015 Issued
Array ( [id] => 10731006 [patent_doc_number] => 20160077156 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT' [patent_app_type] => utility [patent_app_number] => 14/939100 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 82 [patent_no_of_words] => 41511 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14939100 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/939100
TMS/TDI and SIPO controller circuitry with tap and trace interfaces Nov 11, 2015 Issued
Array ( [id] => 11845755 [patent_doc_number] => 09733306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Remote evaluation tool' [patent_app_type] => utility [patent_app_number] => 14/935644 [patent_app_country] => US [patent_app_date] => 2015-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14935644 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/935644
Remote evaluation tool Nov 8, 2015 Issued
Array ( [id] => 11096306 [patent_doc_number] => 20160293275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE OUTPUTTING STATUS FAIL SIGNAL AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/845793 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9162 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845793 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/845793
Semiconductor memory device outputting status fail signal and operating method thereof Sep 3, 2015 Issued
Array ( [id] => 10496185 [patent_doc_number] => 20150381207 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'PARALLEL BIT INTERLEAVER' [patent_app_type] => utility [patent_app_number] => 14/843031 [patent_app_country] => US [patent_app_date] => 2015-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 11595 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14843031 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/843031
Parallel bit interleaver Sep 1, 2015 Issued
Array ( [id] => 13198315 [patent_doc_number] => 10114073 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Integrated circuit testing [patent_app_type] => utility [patent_app_number] => 14/827983 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 43 [patent_no_of_words] => 21489 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827983 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827983
Integrated circuit testing Aug 16, 2015 Issued
Array ( [id] => 11259214 [patent_doc_number] => 09484116 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-01 [patent_title] => 'Test system' [patent_app_type] => utility [patent_app_number] => 14/827743 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5960 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14827743 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/827743
Test system Aug 16, 2015 Issued
Array ( [id] => 11459805 [patent_doc_number] => 20170053711 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-23 [patent_title] => 'MULTI-CHANNEL TESTING' [patent_app_type] => utility [patent_app_number] => 14/828144 [patent_app_country] => US [patent_app_date] => 2015-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6534 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14828144 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/828144
Multi-channel testing Aug 16, 2015 Issued
Array ( [id] => 11444558 [patent_doc_number] => 20170045579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-16 [patent_title] => 'CPU BIST TESTING OF INTEGRATED CIRCUITS USING SERIAL WIRE DEBUG' [patent_app_type] => utility [patent_app_number] => 14/826596 [patent_app_country] => US [patent_app_date] => 2015-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4575 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14826596 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/826596
CPU BIST TESTING OF INTEGRATED CIRCUITS USING SERIAL WIRE DEBUG Aug 13, 2015 Abandoned
Menu