Search

Christine Trinh Le Tu

Examiner (ID: 15624, Phone: (571)272-3831 , Office: P/2117 )

Most Active Art Unit
2117
Art Unit(s)
2313, 2117, 2133, 2785, 2138, 2111, 2413, 2784
Total Applications
1748
Issued Applications
1571
Pending Applications
27
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11071042 [patent_doc_number] => 20160268006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/824402 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/824402
MEMORY SYSTEM AND METHOD OF CONTROLLING MEMORY SYSTEM Aug 11, 2015 Abandoned
Array ( [id] => 11811369 [patent_doc_number] => 09715943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods' [patent_app_type] => utility [patent_app_number] => 14/824935 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14824935 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/824935
Semiconductor memory cell multi-write avoidance encoding apparatus, systems and methods Aug 11, 2015 Issued
Array ( [id] => 11855572 [patent_doc_number] => 20170230064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'METHOD FOR TRANSMITTING/RECEIVING DATA BY UE AND UE THEREFOR' [patent_app_type] => utility [patent_app_number] => 15/503479 [patent_app_country] => US [patent_app_date] => 2015-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9884 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15503479 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/503479
Method for transmitting/receiving data by UE and UE therefor Aug 10, 2015 Issued
Array ( [id] => 11063540 [patent_doc_number] => 20160260502 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/820225 [patent_app_country] => US [patent_app_date] => 2015-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7164 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14820225 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/820225
Semiconductor memory device and operation method thereof Aug 5, 2015 Issued
Array ( [id] => 10597973 [patent_doc_number] => 09319072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Parallel bit interleaver' [patent_app_type] => utility [patent_app_number] => 14/804466 [patent_app_country] => US [patent_app_date] => 2015-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 103 [patent_no_of_words] => 20653 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804466 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804466
Parallel bit interleaver Jul 20, 2015 Issued
Array ( [id] => 10438577 [patent_doc_number] => 20150323589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'COMPOSITE INTEGRATED CIRCUITS AND METHODS FOR WIRELESS INTERACTIONS THEREWITH' [patent_app_type] => utility [patent_app_number] => 14/804319 [patent_app_country] => US [patent_app_date] => 2015-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7932 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14804319 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/804319
Composite integrated circuits and methods for wireless interactions therewith Jul 19, 2015 Issued
Array ( [id] => 10438587 [patent_doc_number] => 20150323598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT' [patent_app_type] => utility [patent_app_number] => 14/802685 [patent_app_country] => US [patent_app_date] => 2015-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 82 [patent_figures_cnt] => 82 [patent_no_of_words] => 41603 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14802685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/802685
Trace controller for processor, periphery, address, control, and data lines Jul 16, 2015 Issued
Array ( [id] => 12819928 [patent_doc_number] => 20180165148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => COMPUTER SYSTEM AND COMPUTER SYSTEM CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 15/571050 [patent_app_country] => US [patent_app_date] => 2015-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15571050 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/571050
Computer system and computer system control method Jun 28, 2015 Issued
Array ( [id] => 10454177 [patent_doc_number] => 20150339192 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'CHANNEL ROTATING ERROR CORRECTION CODE' [patent_app_type] => utility [patent_app_number] => 14/740449 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740449 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740449
Channel rotating error correction code Jun 15, 2015 Issued
Array ( [id] => 11933259 [patent_doc_number] => 09800267 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Apparatus and method for transmitting and receiving a quasi-cyclic low density parity check code in a multimedia communication system' [patent_app_type] => utility [patent_app_number] => 14/739825 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 32406 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14739825 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/739825
Apparatus and method for transmitting and receiving a quasi-cyclic low density parity check code in a multimedia communication system Jun 14, 2015 Issued
Array ( [id] => 10787183 [patent_doc_number] => 20160133339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'TEST APPARATUS, TEST SYSTEM AND OPERATING METHOD OF TEST APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/732281 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5230 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14732281 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/732281
Test apparatus, test system and operating method of test apparatus Jun 4, 2015 Issued
Array ( [id] => 10702275 [patent_doc_number] => 20160048422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-18 [patent_title] => 'ERROR DETECTION DEVICE AND ERROR DETECTION METHOD' [patent_app_type] => utility [patent_app_number] => 14/726832 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9217 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14726832 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/726832
ERROR DETECTION DEVICE AND ERROR DETECTION METHOD May 31, 2015 Abandoned
Array ( [id] => 13171911 [patent_doc_number] => 10102070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Information processing system, storage apparatus and storage device [patent_app_type] => utility [patent_app_number] => 15/531795 [patent_app_country] => US [patent_app_date] => 2015-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 16338 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15531795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/531795
Information processing system, storage apparatus and storage device May 31, 2015 Issued
Array ( [id] => 12474996 [patent_doc_number] => 09990250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Single-IC LDPC encoding and decoding implementations [patent_app_type] => utility [patent_app_number] => 14/725812 [patent_app_country] => US [patent_app_date] => 2015-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7602 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14725812 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/725812
Single-IC LDPC encoding and decoding implementations May 28, 2015 Issued
Array ( [id] => 12495402 [patent_doc_number] => 09996419 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-06-12 [patent_title] => Storage system with distributed ECC capability [patent_app_type] => utility [patent_app_number] => 14/708246 [patent_app_country] => US [patent_app_date] => 2015-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 16750 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14708246 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/708246
Storage system with distributed ECC capability May 8, 2015 Issued
Array ( [id] => 10144860 [patent_doc_number] => 09177672 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-03 [patent_title] => 'Methods of operating memory involving identifiers indicating repair of a memory cell' [patent_app_type] => utility [patent_app_number] => 14/700292 [patent_app_country] => US [patent_app_date] => 2015-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14700292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/700292
Methods of operating memory involving identifiers indicating repair of a memory cell Apr 29, 2015 Issued
Array ( [id] => 10125997 [patent_doc_number] => 09160372 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Parallel bit interleaver by applying a cyclic block and a bit permutation process' [patent_app_type] => utility [patent_app_number] => 14/681442 [patent_app_country] => US [patent_app_date] => 2015-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 35 [patent_no_of_words] => 11588 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14681442 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/681442
Parallel bit interleaver by applying a cyclic block and a bit permutation process Apr 7, 2015 Issued
Array ( [id] => 10194076 [patent_doc_number] => 09222980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'IC test circuitry and adapter with data transport control register' [patent_app_type] => utility [patent_app_number] => 14/679315 [patent_app_country] => US [patent_app_date] => 2015-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 182 [patent_figures_cnt] => 300 [patent_no_of_words] => 67631 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14679315 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/679315
IC test circuitry and adapter with data transport control register Apr 5, 2015 Issued
Array ( [id] => 10402467 [patent_doc_number] => 20150287476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'METHOD OF TESTING SEMICONDUCTOR MEMORY DEVICE, TEST DEVICE, AND COMPUTER READABLE RECORDING MEDIUM FOR RECORDING TEST PROGRAM FOR SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/676395 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7967 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676395 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676395
Method of testing semiconductor memory device, test device, and computer readable recording medium for recording test program for semiconductor memory device Mar 31, 2015 Issued
Array ( [id] => 10408164 [patent_doc_number] => 20150293173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'SEMICONDUCTOR DEVICE, DIAGNOSTIC TEST, AND DIAGNOSTIC TEST CIRCUIT' [patent_app_type] => utility [patent_app_number] => 14/676743 [patent_app_country] => US [patent_app_date] => 2015-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 29199 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14676743 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/676743
Semiconductor device, diagnostic test, and diagnostic test circuit Mar 31, 2015 Issued
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